[Intel-gfx] [PATCH] drm/i915/cnl: Dump the right pll registers when dumping pipe config.

[Rodrigo Vivi]

merged to dinq.
thanks for the review.

On Thu, Aug 10, 2017 at 3:45 PM, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> Different from SKL we don't need ctrl1 and cfgcr2, but
> we need to dump cfgcr0 and cfgcr1 instead.
>
> v2: rebase and commit message
>
> Cc: Clint Taylor <clinton.a.taylor at intel.com>
> Cc: Mika Kahola <mika.kahola at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Reviewed-by: Mika Kahola <mika.kahola at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 2f7b0e64f628..a2a3d93d67bd 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2379,6 +2379,15 @@ cnl_get_dpll(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
>         return pll;
>  }
>
> +static void cnl_dump_hw_state(struct drm_i915_private *dev_priv,
> +                             struct intel_dpll_hw_state *hw_state)
> +{
> +       DRM_DEBUG_KMS("dpll_hw_state: "
> +                     "cfgcr0: 0x%x, cfgcr1: 0x%x\n",
> +                     hw_state->cfgcr0,
> +                     hw_state->cfgcr1);
> +}
> +
>  static const struct intel_shared_dpll_funcs cnl_ddi_pll_funcs = {
>         .enable = cnl_ddi_pll_enable,
>         .disable = cnl_ddi_pll_disable,
> @@ -2395,7 +2404,7 @@ static const struct dpll_info cnl_plls[] = {
>  static const struct intel_dpll_mgr cnl_pll_mgr = {
>         .dpll_info = cnl_plls,
>         .get_dpll = cnl_get_dpll,
> -       .dump_hw_state = skl_dump_hw_state,
> +       .dump_hw_state = cnl_dump_hw_state,
>  };
>
>  /**
> --
> 2.13.2
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br