[Intel-gfx] [RFC 1/7] drm/i915: Introduce a bitmap to indicate available PPAT entries

[Zhi Wang]

To introduce the dynamic private PAT management in GVT-g, the host i915
is required to tell GVT-g the unused PAT entries. The available PPAT
entries are showed in a bitmap. For platforms which don't have private
PAT, the bitmap is set to "empty", so GVT-g will not enable private PAT
management function.

Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h     |  3 +++
 drivers/gpu/drm/i915/i915_gem_gtt.c | 13 ++++++++++++-
 2 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 768a92b..79fc680 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2302,6 +2302,9 @@ struct drm_i915_private {
 	DECLARE_HASHTABLE(mm_structs, 7);
 	struct mutex mm_lock;
 
+#define MAX_PPAT_INDEX 8
+	DECLARE_BITMAP(avail_ppat_bitmap, MAX_PPAT_INDEX);
+
 	/* Kernel Modesetting */
 
 	struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 090ceb7..b9665b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -2758,7 +2758,7 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 	      GEN8_PPAT(6, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(2)) |
 	      GEN8_PPAT(7, GEN8_PPAT_WB | GEN8_PPAT_LLCELLC | GEN8_PPAT_AGE(3));
 
-	if (!USES_PPGTT(dev_priv))
+	if (!USES_PPGTT(dev_priv)) {
 		/* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
 		 * so RTL will always use the value corresponding to
 		 * pat_sel = 000".
@@ -2774,6 +2774,17 @@ static void bdw_setup_private_ppat(struct drm_i915_private *dev_priv)
 		 */
 		pat = GEN8_PPAT(0, GEN8_PPAT_UC);
 
+		set_bit(1, dev_priv->avail_ppat_bitmap);
+		set_bit(2, dev_priv->avail_ppat_bitmap);
+		set_bit(3, dev_priv->avail_ppat_bitmap);
+	}
+
+	/* PPAT entries 4 - 7 are unused, mark them available */
+	set_bit(4, dev_priv->avail_ppat_bitmap);
+	set_bit(5, dev_priv->avail_ppat_bitmap);
+	set_bit(6, dev_priv->avail_ppat_bitmap);
+	set_bit(7, dev_priv->avail_ppat_bitmap);
+
 	/* XXX: spec defines this as 2 distinct registers. It's unclear if a 64b
 	 * write would work. */
 	I915_WRITE(GEN8_PRIVATE_PAT_LO, pat);
-- 
2.7.4