[Intel-gfx] [PATCH 1/4] drm/i915/cnl: Introduce initial Cannonlake Workarounds.
Oscar Mateo
oscar.mateo at intel.com
Tue Aug 15 10:54:26 UTC 2017
On 07/05/2017 06:02 PM, Rodrigo Vivi wrote:
> Let's inherit workarounds from previous platforms that
> according to wa_database and BSpec are still valid for
> Cannonlake.
>
> v2: Add missed workarounds.
> v3: Rebase
> v4: Remove bad chunk that was added to rc6 disable. (Ander)
> Also remove A0 W/a that are not needed anymore.
> v5: Rebase on top of CFL.
> v6: Remove empty gen9_init_perctx_bb and gen9_init_indirectctx_bb
> since they don't carry any gen10 related W/a. (by Oscar).
> Also Remove A0 exclusive workaround.
>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++--
> drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> drivers/gpu/drm/i915/intel_engine_cs.c | 19 +++++++++++++++++++
> drivers/gpu/drm/i915/intel_lrc.c | 2 ++
> drivers/gpu/drm/i915/intel_pm.c | 28 ++++++++++++++++++++++------
> 5 files changed, 51 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index de67084..08570a3 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -1880,12 +1880,12 @@ static void gtt_write_workarounds(struct drm_i915_private *dev_priv)
> * called on driver load and after a GPU reset, so you can place
> * workarounds here even if they get overwritten by GPU reset.
> */
> - /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl */
> + /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl */
> if (IS_BROADWELL(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> - else if (IS_GEN9_BC(dev_priv))
> + else if (IS_GEN9_BC(dev_priv) || IS_GEN10(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> else if (IS_GEN9_LP(dev_priv))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 64cc674..2999a2b 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3626,6 +3626,12 @@ enum {
> #define PWM1_GATING_DIS (1 << 13)
>
> /*
> + * GEN10 clock gating regs
> + */
> +#define SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4)
> +#define SARBUNIT_CLKGATE_DIS (1 << 5)
> +
> +/*
> * Display engine regs
> */
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a55cd72..c520a41 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1067,6 +1067,23 @@ static int bxt_init_workarounds(struct intel_engine_cs *engine)
> return 0;
> }
>
> +static int cnl_init_workarounds(struct intel_engine_cs *engine)
> +{
> + struct drm_i915_private *dev_priv = engine->i915;
> + int ret;
> +
> + /* WaInPlaceDecompressionHang:cnl */
> + WA_SET_BIT(GEN9_GAMT_ECO_REG_RW_IA,
> + GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS);
> +
> + /* WaEnablePreemptionGranularityControlByUMD:cnl */
> + ret= wa_ring_whitelist_reg(engine, GEN8_CS_CHICKEN1);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> static int kbl_init_workarounds(struct intel_engine_cs *engine)
> {
> struct drm_i915_private *dev_priv = engine->i915;
> @@ -1187,6 +1204,8 @@ int init_workarounds_ring(struct intel_engine_cs *engine)
> err = glk_init_workarounds(engine);
> else if (IS_COFFEELAKE(dev_priv))
> err = cfl_init_workarounds(engine);
> + else if (IS_CANNONLAKE(dev_priv))
> + err = cnl_init_workarounds(engine);
> else
> err = 0;
> if (err)
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 699868d..8904ad5 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1175,6 +1175,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
> return -EINVAL;
>
> switch (INTEL_GEN(engine->i915)) {
> + case 10:
> + return 0;
> case 9:
> wa_bb_fn[0] = gen9_init_indirectctx_bb;
> wa_bb_fn[1] = gen9_init_perctx_bb;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c3fcadf..df1b608 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -58,24 +58,24 @@
>
> static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> - /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */
> + /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl,cnl */
> I915_WRITE(CHICKEN_PAR1_1,
> I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
>
I think the above Wa#828 (which should be called
WaPSR2MultipleRegionUpdateCorruption) only applies to CNL A0.
> I915_WRITE(GEN8_CONFIG0,
> I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
>
The above (chicken bits in config0 reg) does not seem to be required for
CNL. In fact, bits 1, 2 & 3 are not chicken bits in CNL anymore :(
When applying this patch to the latest drm-tip, I've also noticed there
is a new display WA#0390 from Ville here. I believe it applies to CNL as
well, so maybe it only requires adding the "cnl" tag to it (+Ville to
confirm).
> - /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */
> + /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl,cnl */
> I915_WRITE(GEN8_CHICKEN_DCPR_1,
> I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>
> - /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */
> - /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */
> + /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl,cnl */
> + /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl,cnl */
> I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
> DISP_FBC_WM_DIS |
> DISP_FBC_MEMORY_WAKE);
>
I have WaFbcTurnOffFbcWatermark only until CNL A0, but at the same time
it's marked as permanent WA.
> - /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */
> + /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl,cnl */
> I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> ILK_DPFC_DISABLE_DUMMY0);
Again, I have this only until CNL A0, but at the same time it's marked
as permanent WA.
> }
> @@ -8226,6 +8226,20 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
> I915_WRITE(GEN7_MISCCPCTL, misccpctl);
> }
>
> +static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv)
> +{
> + gen9_init_clock_gating(dev_priv);
> +
> + /* WaFbcNukeOnHostModify:cnl */
> + I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
> + ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
This should have been fixed in B0.
> + /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */
> + if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
> + I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, I915_READ(SLICE_UNIT_LEVEL_CLKGATE) |
> + SARBUNIT_CLKGATE_DIS);
> +}
> +
> static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
> {
> gen9_init_clock_gating(dev_priv);
> @@ -8706,7 +8720,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
> */
> void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
> {
> - if (IS_SKYLAKE(dev_priv))
> + if (IS_CANNONLAKE(dev_priv))
> + dev_priv->display.init_clock_gating = cannonlake_init_clock_gating;
> + else if (IS_SKYLAKE(dev_priv))
> dev_priv->display.init_clock_gating = skylake_init_clock_gating;
> else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv))
> dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
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