[Intel-gfx] [RFC 6/7] drm/i915/gvt: Introduce virtual private PAT support

[Zhi Wang]

Yes. They will be removed after this feature checked-in. The discussion 
before is at least host should provide all collections of cache 
attribute so we will have a partial match.

On 08/16/17 13:18, Zhenyu Wang wrote:
> On 2017.08.16 05:31:14 +0800, Zhi Wang wrote:
>> Introduce PPAT MMIO handlers. The mapping between virtual PPAT indexes
>> and physical PPAT indexes needs to be re-built after a guest write its
>> virtual PPAT configuration.
>>
>> Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
>> ---
>>   drivers/gpu/drm/i915/gvt/gtt.c      | 26 ++++++++++++++++++++++++++
>>   drivers/gpu/drm/i915/gvt/gtt.h      |  4 +++-
>>   drivers/gpu/drm/i915/gvt/handlers.c | 16 ++++++++++++++--
>>   3 files changed, 43 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
>> index 1d7077d..6ec2a03 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.c
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.c
>> @@ -2374,6 +2374,32 @@ static void put_private_pat_index(struct intel_gvt *gvt, unsigned int index)
>>   		set_bit(index, gtt->avail_ppat_bitmap);
>>   }
>>   
>> +int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu)
>> +{
>> +	struct intel_gvt *gvt = vgpu->gvt;
>> +	struct intel_gvt_gtt_pat_ops *ops = gvt->gtt.pat_ops;
>> +	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
>> +	unsigned int value;
>> +	void *mem = &vgpu_vreg(vgpu, GEN8_PRIVATE_PAT_LO);
>> +	int i;
>> +
>> +	if (gtt->ppat_configured) {
>> +		/* Release all indexes first */
>> +		for (i = 0; i < gvt->gtt.max_ppat_index; i++)
>> +			put_private_pat_index(gvt, gtt->ppat_index[i]);
>> +	}
>> +
>> +	for (i = 0; i < gvt->gtt.max_ppat_index; i++) {
>> +		value = ops->get_pat_value(mem, i, NULL);
>> +		gtt->ppat_index[i] = get_private_pat_index(gvt, value);
>> +	}
> 
> Looks those part in 4/7 should be in this one for easier review.
> 
> And how to handle if really no ppat entry available? Should we define
> some PV interface for guest on sane usage? And as with this new handler
> for PPAT regs, should remove that from save/restore list too?
> 
>> +
>> +	retire_vgpu_ppgtt_mm(vgpu);
>> +
>> +	gtt->ppat_configured = true;
>> +	return 0;
>> +}
>> +
>>   /**
>>    * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
>>    * @vgpu: a vGPU
>> diff --git a/drivers/gpu/drm/i915/gvt/gtt.h b/drivers/gpu/drm/i915/gvt/gtt.h
>> index a83d1f0..ab3e771 100644
>> --- a/drivers/gpu/drm/i915/gvt/gtt.h
>> +++ b/drivers/gpu/drm/i915/gvt/gtt.h
>> @@ -223,7 +223,8 @@ struct intel_vgpu_gtt {
>>   	struct list_head oos_page_list_head;
>>   	struct list_head post_shadow_list_head;
>>   	struct intel_vgpu_scratch_pt scratch_pt[GTT_TYPE_MAX];
>> -
>> +	bool ppat_configured;
>> +	unsigned int ppat_index[MAX_PPAT_INDEX];
>>   };
>>   
>>   extern int intel_vgpu_init_gtt(struct intel_vgpu *vgpu);
>> @@ -234,6 +235,7 @@ extern int intel_gvt_init_gtt(struct intel_gvt *gvt);
>>   void intel_vgpu_reset_gtt(struct intel_vgpu *vgpu);
>>   extern void intel_gvt_clean_gtt(struct intel_gvt *gvt);
>>   
>> +extern int intel_vgpu_update_virtual_ppat(struct intel_vgpu *vgpu);
>>   extern struct intel_vgpu_mm *intel_gvt_find_ppgtt_mm(struct intel_vgpu *vgpu,
>>   		int page_table_level, void *root_entry);
>>   
>> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
>> index 825abfc..e07264f 100644
>> --- a/drivers/gpu/drm/i915/gvt/handlers.c
>> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
>> @@ -1369,6 +1369,18 @@ static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
>>   	return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
>>   }
>>   
>> +static int gen8_ppat_write(struct intel_vgpu *vgpu, unsigned int offset,
>> +		void *p_data, unsigned int bytes)
>> +{
>> +	int ret;
>> +
>> +	ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
>> +	if (ret)
>> +		return ret;
>> +
>> +	return intel_vgpu_update_virtual_ppat(vgpu);
>> +}
>> +
>>   static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
>>   		unsigned int offset, void *p_data, unsigned int bytes)
>>   {
>> @@ -2543,8 +2555,8 @@ static int init_broadwell_mmio_info(struct intel_gvt *gvt)
>>   
>>   	MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
>>   
>> -	MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
>> -	MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
>> +	MMIO_DH(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS, NULL, gen8_ppat_write);
>> +	MMIO_DH(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS, NULL, gen8_ppat_write);
>>   
>>   	MMIO_D(GAMTARBMODE, D_BDW_PLUS);
>>   
>> -- 
>> 2.7.4
>>
>