[Intel-gfx] [PATCH 2/2] drm/i915: Introduce HAS_2PPC.

[Rodrigo Vivi]

Let's make it easier to add platforms that supports 2 pixel per
clock.

With spread checks per platform it was easy to miss one or
another spot leading to loose some time on debug.

Hopefully this check would save some cases in the future.

No functional change.

Cc: Paulo Zanoni <paulo.r.zanoni at intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h    | 4 ++++
 drivers/gpu/drm/i915/i915_pci.c    | 2 ++
 drivers/gpu/drm/i915/intel_cdclk.c | 8 ++++----
 drivers/gpu/drm/i915/intel_pm.c    | 3 +--
 4 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6c25c8520c87..94f5e6522e5e 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -748,6 +748,7 @@ struct intel_csr {
 	func(is_lp); \
 	func(is_alpha_support); \
 	/* Keep has_* in alphabetical order */ \
+	func(has_2ppc); \
 	func(has_64bit_reloc); \
 	func(has_aliasing_ppgtt); \
 	func(has_csr); \
@@ -3025,6 +3026,9 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
 	(IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv))
 
+/* Supports 2 pixel per clock */
+#define HAS_2PPC(dev_priv) ((dev_priv)->info.has_2ppc)
+
 /*
  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
  * even when in MSI mode. This results in spurious interrupt warnings if the
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 09d97e0990b7..df84025579cf 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -405,6 +405,7 @@ static const struct intel_device_info intel_geminilake_info = {
 	GEN9_LP_FEATURES,
 	.platform = INTEL_GEMINILAKE,
 	.ddb_size = 1024,
+	.has_2ppc = 1,
 	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 };
 
@@ -450,6 +451,7 @@ static const struct intel_device_info intel_cannonlake_info = {
 	.gen = 10,
 	.ddb_size = 1024,
 	.has_csr = 1,
+	.has_2ppc = 1,
 	.color = { .degamma_lut_size = 0, .gamma_lut_size = 1024 }
 };
 
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 6b1d805fb755..edbccda40f0c 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1752,7 +1752,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 	    crtc_state->has_audio &&
 	    crtc_state->port_clock >= 540000 &&
 	    crtc_state->lane_count == 4) {
-		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
+		if (HAS_2PPC(dev_priv))
 			pixel_rate = max(2 * 316800, pixel_rate);
 		else
 			pixel_rate = max(432000, pixel_rate);
@@ -1764,7 +1764,7 @@ static int bdw_adjust_min_pipe_pixel_rate(struct intel_crtc_state *crtc_state,
 	 * two pixels per clock.
 	 */
 	if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9) {
-		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv))
+		if (HAS_2PPC(dev_priv))
 			pixel_rate = max(2 * 2 * 96000, pixel_rate);
 		else
 			pixel_rate = max(2 * 96000, pixel_rate);
@@ -1997,14 +1997,14 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
 {
 	int max_cdclk_freq = dev_priv->max_cdclk_freq;
 
-	if (IS_CANNONLAKE(dev_priv))
-		return 2 * max_cdclk_freq;
 	if (IS_GEMINILAKE(dev_priv))
 		/*
 		 * FIXME: Limiting to 99% as a temporary workaround. See
 		 * glk_calc_cdclk() for details.
 		 */
 		return 2 * max_cdclk_freq * 99 / 100;
+	else if (HAS_2PPC(dev_priv))
+		return 2 * max_cdclk_freq;
 	else if (INTEL_INFO(dev_priv)->gen >= 9 ||
 		 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
 		return max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 42f753df30cb..c8da6ca4e8df 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3969,8 +3969,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	crtc_clock = crtc_state->adjusted_mode.crtc_clock;
 	dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk;
 
-	if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev)) ||
-	    IS_CANNONLAKE(to_i915(intel_crtc->base.dev)))
+	if (HAS_2PPC(to_i915(intel_crtc->base.dev)))
 		dotclk *= 2;
 
 	pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
-- 
2.13.2