[Intel-gfx] [PATCH 4/4] drm/i915/cnl: Apply large line width optimization

[Rodrigo Vivi]

patches merged to dinq
thanks for the reviews

On Fri, Aug 18, 2017 at 6:39 AM, Oscar Mateo <oscar.mateo at intel.com> wrote:
>
>
> On 08/15/2017 04:16 PM, Rodrigo Vivi wrote:
>>
>> From: Ben Widawsky <benjamin.widawsky at intel.com>
>>
>> This bit enables hardware that will change the approximation used for
>> distances
>> calculations for AA wide lines so that they are rendered more accurately.
>>
>> The default value for this bit leaves the legacy behavior. There is no
>> good
>> reason to not enable the new approximation except if comparing to previous
>> GEN
>> rendered images.
>>
>> v2: Rebase
>> v3: Fix author.
>>      Rebased by Rodrigo who also added  a comment as suggested by Oscar.
>>      Since it is surrounded by Workarounds let's just add a comment to
>>      make clear it is not an Wa.
>>
>> Cc: Oscar Mateo <oscar.mateo at intel.com>
>> Signed-off-by: Ben Widawsky <benjamin.widawsky at intel.com>
>> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>> ---
>
>
> Reviewed-by: Oscar Mateo <oscar.mateo at intel.com>
>
>
>>   drivers/gpu/drm/i915/i915_reg.h | 1 +
>>   drivers/gpu/drm/i915/intel_pm.c | 4 ++++
>>   2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index 11d5cb690c9c..48b847ddc09a 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -2490,6 +2490,7 @@ enum i915_power_well_id {
>>   # define _3D_CHICKEN2_WM_READ_PIPELINED                       (1 << 14)
>>   #define _3D_CHICKEN3  _MMIO(0x2090)
>>   #define  _3D_CHICKEN_SF_DISABLE_OBJEND_CULL           (1 << 10)
>> +#define  _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE       (1 << 5)
>>   #define  _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL                (1 << 5)
>>   #define  _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x)     ((x)<<1) /* gen8+
>> */
>>   #define  _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6
>> */
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c
>> b/drivers/gpu/drm/i915/intel_pm.c
>> index 5d2d248d4c9e..30eb34979917 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -8256,6 +8256,10 @@ static void gen8_set_l3sqc_credits(struct
>> drm_i915_private *dev_priv,
>>     static void cannonlake_init_clock_gating(struct drm_i915_private
>> *dev_priv)
>>   {
>> +       /* This is not an Wa. Enable for better image quality */
>> +       I915_WRITE(_3D_CHICKEN3,
>> +
>> _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE));
>> +
>>         /* WaEnableChickenDCPR:cnl */
>>         I915_WRITE(GEN8_CHICKEN_DCPR_1,
>>                    I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
>
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br