[Intel-gfx] [PATCH] drm/i915/cnl: WaForceContextSaveRestoreNonCoherent

[Rodrigo Vivi]

patch merged to dinq. thanks for the review and suggestion.


On Wed, Aug 23, 2017 at 1:35 PM, Rodrigo Vivi <rodrigo.vivi at intel.com> wrote:
> To avoid a potential hang condition with TLB invalidation
> we need to enable masked bit 5 of MMIO 0xE5F0 at boot.
>
> Same workaround was in place for previous platforms,
> but the register offset has changed for CNL.
> But also BSpec doesn't mention the bit 15 as set on gen9
> platforms and mark bit as reserved on CNL.
>
> v2: Improve commit message accepting Oscar's suggestion.
>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Reviewed-by: Oscar Mateo <oscar.mateo at intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20170822232715.3220-1-rodrigo.vivi@intel.com

with proper link fixed when merging, instead of this one...

> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 4 ++++
>  2 files changed, 5 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index d9b0249fe5a1..c59c590e45c4 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7024,6 +7024,7 @@ enum {
>
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0                           _MMIO(0x7300)
> +#define CNL_HDC_CHICKEN0                       _MMIO(0xE5F0)
>  #define  HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE        (1<<15)
>  #define  HDC_FENCE_DEST_SLM_DISABLE            (1<<14)
>  #define  HDC_DONOT_FETCH_MEM_WHEN_MASKED       (1<<11)
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index d7e1ccf778a2..a6ac9d0a4156 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1070,6 +1070,10 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>         struct drm_i915_private *dev_priv = engine->i915;
>         int ret;
>
> +       /* WaForceContextSaveRestoreNonCoherent:cnl */
> +       WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> +                         HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +
>         /* WaDisableReplayBufferBankArbitrationOptimization:cnl */
>         WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
>                           GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION);
> --
> 2.13.2
>
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-- 
Rodrigo Vivi
Blog: http://blog.vivi.eng.br