[Intel-gfx] [PATCH] drm/i915/cnl: WaForceEnableNonCoherent

[Oscar Mateo]

On 08/23/2017 03:02 PM, Rodrigo Vivi wrote:
> Must Force Non-Coherent whenever executing a 3D context.
> This is a workaround for a possible hang in the unlikely event
>   a TLB invalidation occurs during a PSD flush.
> Set masked bit 4 in 0x7300 during boot.

This bug should not be present in HW anymore. A different reason to keep 
doing this is performance, though.

> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>   drivers/gpu/drm/i915/intel_engine_cs.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index a6ac9d0a4156..7dfc78b038c4 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1071,8 +1071,11 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>   	int ret;
>   
>   	/* WaForceContextSaveRestoreNonCoherent:cnl */
> +	/* WaForceEnableNonCoherent:cnl */
>   	WA_SET_BIT_MASKED(CNL_HDC_CHICKEN0,
> -			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT);
> +			  HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT |
> +			  HDC_FORCE_NON_COHERENT);
> +
>   
>   	/* WaDisableReplayBufferBankArbitrationOptimization:cnl */
>   	WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,