[Intel-gfx] [PATCH 2/4] drm/i915: decouple gen9 and gen10 dp signal levels.

[Ville Syrjälä]

On Wed, Aug 16, 2017 at 01:19:49PM -0700, Rodrigo Vivi wrote:
> Let's decouple bxt, glk and cnl dp signal levels
> from other DDIs to avoid confusion.
> 
> No functional change. Only a reorg to avoid messing
> with currently working DP signal levels when
> moving voltage swing sequences around to match spec.
> 
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 26 ++++++++++++++++----------
>  drivers/gpu/drm/i915/intel_dp.c  | 10 ++++------
>  drivers/gpu/drm/i915/intel_drv.h |  1 +
>  3 files changed, 21 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index dd2bdbe82b47..9891ad40d1dc 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -2063,23 +2063,29 @@ static uint32_t intel_ddi_dp_level(struct intel_dp *intel_dp)
>  	return translate_signal_level(signal_levels);
>  }
>  
> -uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
> +u32 bxt_signal_levels(struct intel_dp *intel_dp)
>  {
>  	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
>  	struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
>  	struct intel_encoder *encoder = &dport->base;
>  	enum port port = dport->port;
> -	uint32_t level = intel_ddi_dp_level(intel_dp);
> +	u32 level = intel_ddi_dp_level(intel_dp);
>  
> -	if (IS_GEN9_BC(dev_priv))
> -		skl_ddi_set_iboost(encoder, level);
> -	else if (IS_GEN9_LP(dev_priv))
> -		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> -	else if (IS_CANNONLAKE(dev_priv)) {
> +	if (IS_CANNONLAKE(dev_priv))
>  		cnl_ddi_vswing_sequence(encoder, level);
> -		/* DDI_BUF_CTL bits 27:24 are reserved on CNL */
> -		return 0;
> -	}
> +	else
> +		bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
> +
> +	return 0;
> +}
> +
> +uint32_t ddi_signal_levels(struct intel_dp *intel_dp)

skl_signal_levels() perhaps?

> +{
> +	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
> +	struct intel_encoder *encoder = &dport->base;
> +	uint32_t level = intel_ddi_dp_level(intel_dp);
> +
> +	skl_ddi_set_iboost(encoder, level);
>  	return DDI_BUF_TRANS_SELECT(level);
>  }
>  
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4fd4853b2250..1af4b227e758 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3506,13 +3506,11 @@ intel_dp_set_signal_levels(struct intel_dp *intel_dp)
>  	uint32_t signal_levels, mask = 0;
>  	uint8_t train_set = intel_dp->train_set[0];
>  
> -	if (HAS_DDI(dev_priv)) {
> +	if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> +		signal_levels = bxt_signal_levels(intel_dp);
> +	} else if (HAS_DDI(dev_priv)) {
>  		signal_levels = ddi_signal_levels(intel_dp);
> -
> -		if (IS_GEN9_LP(dev_priv) || IS_CANNONLAKE(dev_priv))
> -			signal_levels = 0;
> -		else
> -			mask = DDI_BUF_EMP_MASK;
> +		mask = DDI_BUF_EMP_MASK;
>  	} else if (IS_CHERRYVIEW(dev_priv)) {
>  		signal_levels = chv_signal_levels(intel_dp);
>  	} else if (IS_VALLEYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index fa47285918f4..913cccc54ad2 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1272,6 +1272,7 @@ void intel_ddi_clock_get(struct intel_encoder *encoder,
>  			 struct intel_crtc_state *pipe_config);
>  void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state,
>  				    bool state);
> +u32 bxt_signal_levels(struct intel_dp *intel_dp);
>  uint32_t ddi_signal_levels(struct intel_dp *intel_dp);
>  u8 intel_ddi_dp_voltage_max(struct intel_encoder *encoder);
>  
> -- 
> 2.13.2

-- 
Ville Syrjälä
Intel OTC