[Intel-gfx] [i-g-t PATCH 08/10] tools/intel_vbt_decode: migrate edp dumping to kernel struct
Jani Nikula
jani.nikula at intel.com
Mon Aug 28 12:20:00 UTC 2017
No functional changes.
Signed-off-by: Jani Nikula <jani.nikula at intel.com>
---
tools/intel_bios.h | 33 ---------------------------------
tools/intel_vbt_decode.c | 7 ++++---
tools/intel_vbt_defs.h | 35 +++++++++++++++++++++++++++++++++++
3 files changed, 39 insertions(+), 36 deletions(-)
diff --git a/tools/intel_bios.h b/tools/intel_bios.h
index f4b0b9795221..9f0bc84f372c 100644
--- a/tools/intel_bios.h
+++ b/tools/intel_bios.h
@@ -130,39 +130,6 @@ struct edp_power_seq {
uint16_t t12;
} __attribute__ ((packed));
-struct edp_fast_link_params {
- uint8_t rate:4;
- uint8_t lanes:4;
- uint8_t preemphasis:4;
- uint8_t vswing:4;
-} __attribute__ ((packed));
-
-struct edp_pwm_delays {
- uint16_t pwm_on_to_backlight_enable;
- uint16_t backlight_disable_to_pwm_off;
-} __attribute__ ((packed));
-
-struct edp_full_link_params {
- uint8_t preemphasis:4;
- uint8_t vswing:4;
-} __attribute__ ((packed));
-
-struct bdb_edp { /* 155 */
- struct edp_power_seq power_seqs[16];
- uint32_t color_depth;
- struct edp_fast_link_params fast_link_params[16];
- uint32_t sdrrs_msa_timing_delay;
-
- uint16_t s3d_feature; /* 163 */
- uint16_t t3_optimization; /* 165 */
- uint64_t vswing_preemph_table_selection; /* 173 */
- uint16_t fast_link_training; /* 182 */
- uint16_t dpcd_600h_write_required; /* 185 */
- struct edp_pwm_delays pwm_delays[16]; /* 186 */
- uint16_t full_link_params_provided; /* 199 */
- struct edp_full_link_params full_link_params[16]; /* 199 */
-} __attribute__ ((packed));
-
/* Block 52 contains MiPi Panel info
* 6 such enteries will there. Index into correct
* entery is based on the panel_index in #40 LFP
diff --git a/tools/intel_vbt_decode.c b/tools/intel_vbt_decode.c
index d0b91a3de3ef..ed0b90bd63e6 100644
--- a/tools/intel_vbt_decode.c
+++ b/tools/intel_vbt_decode.c
@@ -44,6 +44,7 @@
typedef uint8_t u8;
typedef uint16_t u16;
typedef uint32_t u32;
+typedef uint64_t u64;
#define __packed __attribute__ ((packed))
#define _INTEL_BIOS_PRIVATE
@@ -797,17 +798,17 @@ static void dump_edp(struct context *context,
}
if (context->bdb->version >= 162) {
- bool val = (edp->s3d_feature >> i) & 1;
+ bool val = (edp->edp_s3d_feature >> i) & 1;
printf("\t\tStereo 3D feature: %s\n", YESNO(val));
}
if (context->bdb->version >= 165) {
- bool val = (edp->t3_optimization >> i) & 1;
+ bool val = (edp->edp_t3_optimization >> i) & 1;
printf("\t\tT3 optimization: %s\n", YESNO(val));
}
if (context->bdb->version >= 173) {
- int val = (edp->vswing_preemph_table_selection >> (i * 4)) & 0xf;
+ int val = (edp->edp_vswing_preemph >> (i * 4)) & 0xf;
printf("\t\tVswing/preemphasis table selection: ");
switch (val) {
diff --git a/tools/intel_vbt_defs.h b/tools/intel_vbt_defs.h
index a43ec2d1c02e..9513f9dc21ab 100644
--- a/tools/intel_vbt_defs.h
+++ b/tools/intel_vbt_defs.h
@@ -671,6 +671,41 @@ struct bdb_driver_features {
#define EDP_VSWING_0_8V 2
#define EDP_VSWING_1_2V 3
+
+struct edp_fast_link_params {
+ u8 rate:4;
+ u8 lanes:4;
+ u8 preemphasis:4;
+ u8 vswing:4;
+} __packed;
+
+struct edp_pwm_delays {
+ u16 pwm_on_to_backlight_enable;
+ u16 backlight_disable_to_pwm_off;
+} __packed;
+
+struct edp_full_link_params {
+ u8 preemphasis:4;
+ u8 vswing:4;
+} __packed;
+
+struct bdb_edp {
+ struct edp_power_seq power_seqs[16];
+ u32 color_depth;
+ struct edp_fast_link_params fast_link_params[16];
+ u32 sdrrs_msa_timing_delay;
+
+ /* ith bit indicates enabled/disabled for (i+1)th panel */
+ u16 edp_s3d_feature; /* 162 */
+ u16 edp_t3_optimization; /* 165 */
+ u64 edp_vswing_preemph; /* 173 */
+ u16 fast_link_training; /* 182 */
+ u16 dpcd_600h_write_required; /* 185 */
+ struct edp_pwm_delays pwm_delays[16]; /* 186 */
+ u16 full_link_params_provided; /* 199 */
+ struct edp_full_link_params full_link_params[16]; /* 199 */
+} __packed;
+
struct psr_table {
/* Feature bits */
u8 full_link:1;
--
2.11.0
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