[Intel-gfx] [PATCH] drm/i915: Keep the device awake whilst in the GTT write domain

[Chris Wilson]

Since runtime suspend is very harsh on GTT mmappings (they all get
zapped on suspend) keep the device awake while we the buffer remains in
the GTT write domain (as we expect subsequent writes). We special case
writes here, as the write domain is more bounded than the read domains;
a buffer may remain in multiple read domains until it is written to, but
a write from the GTT must be flushed prior to using it elsewhere (e.g.
on the GPU). However, userspace can control the write-domain and
although there is a soft contract that writes must be flushed (for e.g.
flushing scanouts and fbc), in the worst case an idle buffer may keep the
device alive until the buffer is destroyed.
---
 drivers/gpu/drm/i915/i915_gem.c            | 4 ++--
 drivers/gpu/drm/i915/i915_gem_execbuffer.c | 2 ++
 2 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index e4cc08bc518c..a87ef5c77a92 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -695,15 +695,14 @@ flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains)
 	switch (obj->base.write_domain) {
 	case I915_GEM_DOMAIN_GTT:
 		if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) {
-			intel_runtime_pm_get(dev_priv);
 			spin_lock_irq(&dev_priv->uncore.lock);
 			POSTING_READ_FW(RING_ACTHD(dev_priv->engine[RCS]->mmio_base));
 			spin_unlock_irq(&dev_priv->uncore.lock);
-			intel_runtime_pm_put(dev_priv);
 		}
 
 		intel_fb_obj_flush(obj,
 				   fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
+		intel_runtime_pm_put(dev_priv);
 		break;
 
 	case I915_GEM_DOMAIN_CPU:
@@ -3555,6 +3554,7 @@ i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
 	GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
 	obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
 	if (write) {
+		intel_runtime_pm_get_noresume(to_i915(obj->base.dev));
 		obj->base.read_domains = I915_GEM_DOMAIN_GTT;
 		obj->base.write_domain = I915_GEM_DOMAIN_GTT;
 		obj->mm.dirty = true;
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index 8a9d37ac16d4..62c215eb38b7 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -1865,6 +1865,8 @@ void i915_vma_move_to_active(struct i915_vma *vma,
 	i915_gem_active_set(&vma->last_read[idx], req);
 	list_move_tail(&vma->vm_link, &vma->vm->active_list);
 
+	if (obj->base.write_domain & I915_GEM_DOMAIN_GTT)
+		intel_runtime_pm_put(to_i915(obj->base.dev));
 	obj->base.write_domain = 0;
 	if (flags & EXEC_OBJECT_WRITE) {
 		obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
-- 
2.14.1