[Intel-gfx] [PATCH v2] drm/i915: Fix deadlock in i830_disable_pipe()
Ville Syrjälä
ville.syrjala at linux.intel.com
Fri Dec 1 15:12:05 UTC 2017
On Wed, Nov 29, 2017 at 02:54:11PM +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
>
> i830_disable_pipe() gets called from the power well code, and thus
> we're already holding the power domain mutex. That means we can't
> call plane->get_hw_state() as it will also try to grab the
> same mutex and will thus deadlock.
>
> Replace the assert_plane() calls (which calls ->get_hw_state()) with
> just raw register reads in i830_disable_pipe(). As a bonus we can
> now get a warning if plane C is enabled even though we don't even
> expose it as a drm plane.
>
> v2: Do a separate WARN_ON() for each plane (Chris)
>
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
> Fixes: 51f5a0963984 ("drm/i915: Add .get_hw_state() method for planes")
> Signed-off-by: Ville Syrjälä <ville.syrjala at linux.intel.com>
Pushed to dinq. Thanks for the review.
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index d67c7c498b34..674b86bbe7d7 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14731,8 +14731,11 @@ void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
> DRM_DEBUG_KMS("disabling pipe %c due to force quirk\n",
> pipe_name(pipe));
>
> - assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_A));
> - assert_planes_disabled(intel_get_crtc_for_pipe(dev_priv, PIPE_B));
> + WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE);
> + WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE);
> + WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE);
> + WARN_ON(I915_READ(CURCNTR(PIPE_A)) & CURSOR_MODE);
> + WARN_ON(I915_READ(CURCNTR(PIPE_B)) & CURSOR_MODE);
>
> I915_WRITE(PIPECONF(pipe), 0);
> POSTING_READ(PIPECONF(pipe));
> --
> 2.13.6
--
Ville Syrjälä
Intel OTC
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