[Intel-gfx] [PATCH v5] drm/i915: Restore GT performance in headless mode with DMC loaded

Sat Dec 2 00:05:42 UTC 2017

On Thu, 2017-11-30 at 13:19 +0200, Imre Deak wrote:
> > > +#define NEEDS_CSR_GT_PERF_WA(dev_priv) \
> > > +       (HAS_CSR(dev_priv) && IS_GEN9(dev_priv) && !
> IS_SKYLAKE(dev_priv))
> 
> Nitpick: could be just !IS_SKYLAKE(), but works in the above way too.
> For all other platforms the GT_IRQ domain won't be mapped making
> display_power_get/put on those just a domain ref inc/dec, otherwise a
> nop.

Why not +&& !IS_BROXTON(dev_priv) by the way?