[Intel-gfx] [PATCH 2/2] drm/i915: Assert GGTT writes were flushed before unbinding a GGTT vma

[Chris Wilson]

As writes through the GTT and GGTT PTE updates do not share the same
path, they are not strictly ordered and so we must explicitly flush the
indirect writes prior to modifying the PTE. However, we track the PTE
using multiple vma, but only a single write_domain on the object, so
before unbinding any GGTT vma we must flush all writes. Provide an
assert that this is so.

Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
---
 drivers/gpu/drm/i915/i915_vma.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index bf6d8d1eaabe..846056cd1eb7 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -790,6 +790,14 @@ int i915_vma_unbind(struct i915_vma *vma)
 	GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj));
 
 	if (i915_vma_is_map_and_fenceable(vma)) {
+		/*
+		 * Check that we have flushed all writes through the GGTT
+		 * before the unbind. We don't track writes per-vma so assume
+		 * that we have flushed all writes on the object before each
+		 * GGTT vma is unbound.
+		 */
+		GEM_BUG_ON(obj->base.write_domain & I915_GEM_DOMAIN_GTT);
+
 		/* release the fence reg _after_ flushing */
 		ret = i915_vma_put_fence(vma);
 		if (ret)
-- 
2.15.1