[Intel-gfx] [PATCH v6] drm/i915: Restore GT performance in headless mode with DMC loaded

[Chris Wilson]

Quoting Tvrtko Ursulin (2017-12-05 13:28:54)
> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> 
> It seems that the DMC likes to transition between the DC states a lot when
> there are no connected displays (no active power domains) during command
> submission.
> 
> This activity on DC states has a negative impact on the performance of the
> chip with huge latencies observed in the interrupt handlers and elsewhere.
> Simple tests like igt/gem_latency -n 0 are slowed down by a factor of
> eight.
> 
> Work around it by introducing a new power domain named,
> POWER_DOMAIN_GT_IRQ, associtated with the "DC off" power well, which is
> held for the duration of command submission activity.
> 
> v2:
>  * Add commit text as comment in i915_gem_mark_busy. (Chris Wilson)
>  * Protect macro body with braces. (Jani Nikula)
> 
> v3:
>  * Add dedicated power domain for clarity. (Chris, Imre)
>  * Commit message and comment text updates.
>  * Apply to all big-core GEN9 parts apart for Skylake which is pending DMC
>    firmware release.
> 
> v4:
>  * Power domain should be inner to device runtime pm. (Chris)
>  * Simplify NEEDS_CSR_GT_PERF_WA macro. (Chris)
>  * Handle async DMC loading by moving the GT_IRQ power domain logic into
>    intel_runtime_pm. (Daniel, Chris)
>  * Include small core GEN9 as well. (Imre)
> 
> v5
>  * Special handling for async DMC load is not needed since on failure the
>    power domain reference is kept permanently taken. (Imre)
> 
> v6:
>  * Drop the NEEDS_CSR_GT_PERF_WA macro since all firmwares have now been
>    deployed. (Imre, Chris)
> 
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100572
> Testcase: igt/gem_exec_nop/headless
> Cc: Imre Deak <imre.deak at intel.com>
> Acked-by: Chris Wilson <chris at chris-wilson.co.uk> (v2)
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Dmitry Rogozhkin <dmitry.v.rogozhkin at intel.com>
> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch> (v5)
> Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk> (v5)
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>

Could we add a note that Cannonlake is excluded and needs to be checked
as to whether it suffers the same?
-Chris