[Intel-gfx] [PATCH v4 4/9] drm: Add some HDCP related #defines

[Ramalingam C]

Looks Good to me.

Reviewed-by: Ramalingam C <ramalingm.c at intel.com>

-Ram

On Thursday 07 December 2017 05:30 AM, Sean Paul wrote:
> In preparation for implementing HDCP in i915, add some HDCP related
> register offsets and defines. The dpcd register offsets will go in
> drm_dp_helper.h whereas the ddc offsets along with generic HDCP stuff
> will get stuffed in drm_hdcp.h, which is new.
>
> Changes in v2:
> - drm_hdcp.h gets MIT license (Daniel)
> Changes in v3:
> - None
> Changes in v4:
> - None
>
> Cc: Daniel Vetter <daniel.vetter at intel.com>
> Signed-off-by: Sean Paul <seanpaul at chromium.org>
> ---
>   include/drm/drm_dp_helper.h | 17 ++++++++++++++
>   include/drm/drm_hdcp.h      | 56 +++++++++++++++++++++++++++++++++++++++++++++
>   2 files changed, 73 insertions(+)
>   create mode 100644 include/drm/drm_hdcp.h
>
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index 8b9ac321c3bd..4b2640d54c70 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -815,6 +815,23 @@
>   #define DP_CEC_TX_MESSAGE_BUFFER               0x3020
>   #define DP_CEC_MESSAGE_BUFFER_LENGTH             0x10
>   
> +#define DP_AUX_HDCP_BKSV		0x68000
> +#define DP_AUX_HDCP_RI_PRIME		0x68005
> +#define DP_AUX_HDCP_AKSV		0x68007
> +#define DP_AUX_HDCP_AN			0x6800C
> +#define DP_AUX_HDCP_V_PRIME(h)		(0x68014 + h * 4)
> +#define DP_AUX_HDCP_BCAPS		0x68028
> +# define DP_BCAPS_REPEATER_PRESENT	BIT(1)
> +# define DP_BCAPS_HDCP_CAPABLE		BIT(0)
> +#define DP_AUX_HDCP_BSTATUS		0x68029
> +# define DP_BSTATUS_REAUTH_REQ		BIT(3)
> +# define DP_BSTATUS_LINK_FAILURE	BIT(2)
> +# define DP_BSTATUS_R0_PRIME_READY	BIT(1)
> +# define DP_BSTATUS_READY		BIT(0)
> +#define DP_AUX_HDCP_BINFO		0x6802A
> +#define DP_AUX_HDCP_KSV_FIFO		0x6802C
> +#define DP_AUX_HDCP_AINFO		0x6803B
> +
>   /* DP 1.2 Sideband message defines */
>   /* peer device type - DP 1.2a Table 2-92 */
>   #define DP_PEER_DEVICE_NONE		0x0
> diff --git a/include/drm/drm_hdcp.h b/include/drm/drm_hdcp.h
> new file mode 100644
> index 000000000000..c9b2484240d4
> --- /dev/null
> +++ b/include/drm/drm_hdcp.h
> @@ -0,0 +1,56 @@
> +/*
> + * Copyright (C) 2017 Google, Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + * Sean Paul <seanpaul at chromium.org>
> + */
> +
> +#ifndef _DRM_HDCP_H_INCLUDED_
> +#define _DRM_HDCP_H_INCLUDED_
> +
> +/* Period of hdcp checks (to ensure we're still authenticated) */
> +#define DRM_HDCP_CHECK_PERIOD_MS		(128 * 16)
> +
> +/* Shared lengths/masks between HDMI/DVI/DisplayPort */
> +#define DRM_HDCP_AN_LEN				8
> +#define DRM_HDCP_BSTATUS_LEN			2
> +#define DRM_HDCP_KSV_LEN			5
> +#define DRM_HDCP_RI_LEN				2
> +#define DRM_HDCP_V_PRIME_PART_LEN		4
> +#define DRM_HDCP_V_PRIME_NUM_PARTS		5
> +#define DRM_HDCP_NUM_DOWNSTREAM(x)		(x & 0x3f)
> +
> +/* Slave address for the HDCP registers in the receiver */
> +#define DRM_HDCP_DDC_ADDR			0x3A
> +
> +/* HDCP register offsets for HDMI/DVI devices */
> +#define DRM_HDCP_DDC_BKSV			0x00
> +#define DRM_HDCP_DDC_RI_PRIME			0x08
> +#define DRM_HDCP_DDC_AKSV			0x10
> +#define DRM_HDCP_DDC_AN				0x18
> +#define DRM_HDCP_DDC_V_PRIME(h)			(0x20 + h * 4)
> +#define DRM_HDCP_DDC_BCAPS			0x40
> +#define  DRM_HDCP_DDC_BCAPS_REPEATER_PRESENT	BIT(6)
> +#define  DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY	BIT(5)
> +#define DRM_HDCP_DDC_BSTATUS			0x41
> +#define DRM_HDCP_DDC_KSV_FIFO			0x43
> +
> +#endif

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