[Intel-gfx] [GIT PULL] gvt-fixes for 4.15-rc3

[Joonas Lahtinen]

Hi,

Pulled these, I will give it a final go with CI and send the pull forward. Thanks.

Regards, Joonas

On Wed, 2017-12-06 at 15:51 +0800, Zhenyu Wang wrote:
> Hi,
> 
> Here's gvt-fixes for 4.15-rc3 with several fixes backported.
> 
> thanks
> --
> The following changes since commit b721b65af4eb46df6a1d9e34b14003225e403565:
> 
>   drm/i915/gvt: Correct ADDR_4K/2M/1G_MASK definition (2017-11-28 17:24:30 +0800)
> 
> are available in the Git repository at:
> 
>   https://github.com/intel/gvt-linux.git tags/gvt-fixes-2017-12-06
> 
> for you to fetch changes up to 11474e9091cf2002e948647fd9f63a7f027e488a:
> 
>   drm/i915/gvt: set max priority for gvt context (2017-12-06 11:38:21 +0800)
> 
> ----------------------------------------------------------------
> gvt-fixes-2017-12-06
> 
> - Fix invalid hw reg read value for vGPU (Xiong)
> - Fix qemu warning on PCI ROM bar missing (Changbin)
> - Workaround preemption regression (Zhenyu)
> 
> ----------------------------------------------------------------
> Changbin Du (1):
>       drm/i915/gvt: Emulate PCI expansion ROM base address register
> 
> Xiong Zhang (1):
>       drm/i915/gvt: Limit read hw reg to active vgpu
> 
> Zhenyu Wang (2):
>       drm/i915/gvt: Don't mark vgpu context as inactive when preempted
>       drm/i915/gvt: set max priority for gvt context
> 
> Zhi Wang (1):
>       drm/i915/gvt: Export intel_gvt_render_mmio_to_ring_id()
> 
>  drivers/gpu/drm/i915/gvt/cfg_space.c | 21 ++++++++++++++++
>  drivers/gpu/drm/i915/gvt/handlers.c  | 47 ++++++++++++++++++++++++++++--------
>  drivers/gpu/drm/i915/gvt/mmio.h      |  2 ++
>  drivers/gpu/drm/i915/gvt/scheduler.c | 22 ++++++++++++++++-
>  4 files changed, 81 insertions(+), 11 deletions(-)
> 
-- 
Joonas Lahtinen
Open Source Technology Center
Intel Corporation