[Intel-gfx] [PATCH] drm/i915/cfl: Adding more Coffee Lake PCI IDs.

[Anusha Srivatsa]

On Wed, Dec 20, 2017 at 10:29:19AM -0800, Rodrigo Vivi wrote:
> Spec has been updated with more reserved IDs for existent SKUs.
> 
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa at intel.com>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>
> Cc: Anuj Phogat <anuj.phogat at gmail.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
The IDs match with Spec.

Reviewed-by: Anusha Srivatsa<anusha.srivatsa at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_pci.c |  2 ++
>  include/drm/i915_pciids.h       | 28 ++++++++++++++++++++++------
>  2 files changed, 24 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index fa67d3dde20e..36d48422b475 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -633,6 +633,8 @@ static const struct pci_device_id pciidlist[] = {
>  	INTEL_CFL_S_GT1_IDS(&intel_coffeelake_gt1_info),
>  	INTEL_CFL_S_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_CFL_H_GT2_IDS(&intel_coffeelake_gt2_info),
> +	INTEL_CFL_U_GT1_IDS(&intel_coffeelake_gt1_info),
> +	INTEL_CFL_U_GT2_IDS(&intel_coffeelake_gt2_info),
>  	INTEL_CFL_U_GT3_IDS(&intel_coffeelake_gt3_info),
>  	INTEL_CNL_U_GT2_IDS(&intel_cannonlake_gt2_info),
>  	INTEL_CNL_Y_GT2_IDS(&intel_cannonlake_gt2_info),
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index c65e4489006d..5db0458dd832 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -373,29 +373,45 @@
>  /* CFL S */
>  #define INTEL_CFL_S_GT1_IDS(info) \
>  	INTEL_VGA_DEVICE(0x3E90, info), /* SRV GT1 */ \
> -	INTEL_VGA_DEVICE(0x3E93, info)  /* SRV GT1 */
> +	INTEL_VGA_DEVICE(0x3E93, info), /* SRV GT1 */ \
> +	INTEL_VGA_DEVICE(0x3E99, info)  /* SRV GT1 */
>  
>  #define INTEL_CFL_S_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x3E91, info), /* SRV GT2 */ \
>  	INTEL_VGA_DEVICE(0x3E92, info), /* SRV GT2 */ \
> -	INTEL_VGA_DEVICE(0x3E96, info)  /* SRV GT2 */
> +	INTEL_VGA_DEVICE(0x3E96, info), /* SRV GT2 */ \
> +	INTEL_VGA_DEVICE(0x3E9A, info)  /* SRV GT2 */
>  
>  /* CFL H */
>  #define INTEL_CFL_H_GT2_IDS(info) \
>  	INTEL_VGA_DEVICE(0x3E9B, info), /* Halo GT2 */ \
>  	INTEL_VGA_DEVICE(0x3E94, info)  /* Halo GT2 */
>  
> -/* CFL U */
> +/* CFL U GT1 */
> +#define INTEL_CFL_U_GT1_IDS(info) \
> +	INTEL_VGA_DEVICE(0x3EA1, info), \
> +	INTEL_VGA_DEVICE(0x3EA4, info)
> +
> +/* CFL U GT2 */
> +#define INTEL_CFL_U_GT2_IDS(info) \
> +	INTEL_VGA_DEVICE(0x3EA0, info), \
> +	INTEL_VGA_DEVICE(0x3EA3, info), \
> +	INTEL_VGA_DEVICE(0x3EA9, info)
> +
> +/* CFL U GT3 */
>  #define INTEL_CFL_U_GT3_IDS(info) \
> +	INTEL_VGA_DEVICE(0x3EA2, info), /* ULT GT3 */ \
> +	INTEL_VGA_DEVICE(0x3EA5, info), /* ULT GT3 */ \
>  	INTEL_VGA_DEVICE(0x3EA6, info), /* ULT GT3 */ \
>  	INTEL_VGA_DEVICE(0x3EA7, info), /* ULT GT3 */ \
> -	INTEL_VGA_DEVICE(0x3EA8, info), /* ULT GT3 */ \
> -	INTEL_VGA_DEVICE(0x3EA5, info)  /* ULT GT3 */
> +	INTEL_VGA_DEVICE(0x3EA8, info)  /* ULT GT3 */
>  
> -#define INTEL_CFL_IDS(info) \
> +#define INTEL_CFL_IDS(info)	   \
>  	INTEL_CFL_S_GT1_IDS(info), \
>  	INTEL_CFL_S_GT2_IDS(info), \
>  	INTEL_CFL_H_GT2_IDS(info), \
> +	INTEL_CFL_U_GT1_IDS(info), \
> +	INTEL_CFL_U_GT2_IDS(info), \
>  	INTEL_CFL_U_GT3_IDS(info)
>  
>  /* CNL U 2+2 */
> -- 
> 2.13.6
> 

-- 
Anusha Srivatsa