[Intel-gfx] [PATCH] drm/i915/psr: Don't name status or debug registers like control registers.

[Rodrigo Vivi]

On Wed, Dec 20, 2017 at 08:10:21PM +0000, Dhinakaran Pandiyan wrote:
> Avoids some typo pitfalls.
> 
> Cc: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> ---
>  drivers/gpu/drm/i915/i915_debugfs.c |  4 ++--
>  drivers/gpu/drm/i915/i915_reg.h     |  6 +++---
>  drivers/gpu/drm/i915/intel_psr.c    | 24 ++++++++++++------------
>  3 files changed, 17 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index c4780f085428..81ca9433fc9e 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2578,9 +2578,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		seq_printf(m, "Performance_Counter: %u\n", psrperf);
>  	}
>  	if (dev_priv->psr.psr2_support) {
> -		u32 psr2 = I915_READ(EDP_PSR2_STATUS_CTL);
> +		u32 psr2 = I915_READ(EDP_PSR2_STATUS);
>  
> -		seq_printf(m, "EDP_PSR2_STATUS_CTL: %x [%s]\n",
> +		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
>  			   psr2, psr2_live_status(psr2));
>  	}
>  	mutex_unlock(&dev_priv->psr.lock);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 268bbd0eaaa4..db7757a04720 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -4060,7 +4060,7 @@ enum {
>  #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
>  #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
>  
> -#define EDP_PSR_STATUS_CTL			_MMIO(dev_priv->psr_mmio_base + 0x40)
> +#define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
>  #define   EDP_PSR_STATUS_STATE_MASK		(7<<29)
>  #define   EDP_PSR_STATUS_STATE_IDLE		(0<<29)
>  #define   EDP_PSR_STATUS_STATE_SRDONACK		(1<<29)
> @@ -4087,7 +4087,7 @@ enum {
>  #define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
>  #define   EDP_PSR_PERF_CNT_MASK		0xffffff
>  
> -#define EDP_PSR_DEBUG_CTL		_MMIO(dev_priv->psr_mmio_base + 0x60)
> +#define EDP_PSR_DEBUG				_MMIO(dev_priv->psr_mmio_base + 0x60)
>  #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
>  #define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
> @@ -4110,7 +4110,7 @@ enum {
>  #define   EDP_PSR2_IDLE_MASK		0xf
>  #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a)<<4)
>  
> -#define EDP_PSR2_STATUS_CTL            _MMIO(0x6f940)
> +#define EDP_PSR2_STATUS			_MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
>  #define EDP_PSR2_STATUS_STATE_SHIFT    28
>  
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 2e32615eeada..403256ad871d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -476,7 +476,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  			chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
>  		I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>  
> -		I915_WRITE(EDP_PSR_DEBUG_CTL,
> +		I915_WRITE(EDP_PSR_DEBUG,
>  			   EDP_PSR_DEBUG_MASK_MEMUP |
>  			   EDP_PSR_DEBUG_MASK_HPD |
>  			   EDP_PSR_DEBUG_MASK_LPSP |
> @@ -490,7 +490,7 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
>  		 * preventing  other hw tracking issues now we can rely
>  		 * on frontbuffer tracking.
>  		 */
> -		I915_WRITE(EDP_PSR_DEBUG_CTL,
> +		I915_WRITE(EDP_PSR_DEBUG,
>  			   EDP_PSR_DEBUG_MASK_MEMUP |
>  			   EDP_PSR_DEBUG_MASK_HPD |
>  			   EDP_PSR_DEBUG_MASK_LPSP);
> @@ -599,7 +599,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
>  					0);
>  
>  		if (dev_priv->psr.psr2_support) {
> -			psr_status = EDP_PSR2_STATUS_CTL;
> +			psr_status = EDP_PSR2_STATUS;
>  			psr_status_mask = EDP_PSR2_STATUS_STATE_MASK;
>  
>  			I915_WRITE(EDP_PSR2_CTL,
> @@ -607,7 +607,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp,
>  				   ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE));
>  
>  		} else {
> -			psr_status = EDP_PSR_STATUS_CTL;
> +			psr_status = EDP_PSR_STATUS;
>  			psr_status_mask = EDP_PSR_STATUS_STATE_MASK;
>  
>  			I915_WRITE(EDP_PSR_CTL,
> @@ -679,19 +679,19 @@ static void intel_psr_work(struct work_struct *work)
>  	if (HAS_DDI(dev_priv)) {
>  		if (dev_priv->psr.psr2_support) {
>  			if (intel_wait_for_register(dev_priv,
> -						EDP_PSR2_STATUS_CTL,
> -						EDP_PSR2_STATUS_STATE_MASK,
> -						0,
> -						50)) {
> +						    EDP_PSR2_STATUS,
> +						    EDP_PSR2_STATUS_STATE_MASK,
> +						    0,
> +						    50)) {
>  				DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
>  				return;
>  			}
>  		} else {
>  			if (intel_wait_for_register(dev_priv,
> -						EDP_PSR_STATUS_CTL,
> -						EDP_PSR_STATUS_STATE_MASK,
> -						0,
> -						50)) {
> +						    EDP_PSR_STATUS,
> +						    EDP_PSR_STATUS_STATE_MASK,
> +						    0,
> +						    50)) {
>  				DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
>  				return;
>  			}
> -- 
> 2.11.0
>