[Intel-gfx] [PATCH 04/11] drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.

[Pandiyan, Dhinakaran]

On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> This was wrong since its introduction on commit '04416108ccea
> ("drm/i915/cnl: Add registers related to voltage swing sequences.")'
> 
> But since no Port F was needed so far we don't need to
> propagate fixes back there.
> 

Checked against the spec, fix looks correct.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan at intel.com>

> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Cc: Manasi Navare <manasi.d.navare at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 21ebf5178169..7b209f33a81e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1964,7 +1964,7 @@ enum i915_power_well_id {
>  #define _CNL_PORT_TX_DW2_LN0_B		0x162648
>  #define _CNL_PORT_TX_DW2_LN0_C		0x162C48
>  #define _CNL_PORT_TX_DW2_LN0_D		0x162E48
> -#define _CNL_PORT_TX_DW2_LN0_F		0x162A48
> +#define _CNL_PORT_TX_DW2_LN0_F		0x162848
>  #define CNL_PORT_TX_DW2_GRP(port)	_MMIO_PORT6(port, \
>  						    _CNL_PORT_TX_DW2_GRP_AE, \
>  						    _CNL_PORT_TX_DW2_GRP_B, \