[Intel-gfx] [PATCH 05/11] drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.

[Rodrigo Vivi]

On Tue, Dec 26, 2017 at 10:36:51PM +0000, Pandiyan, Dhinakaran wrote:
> 
> 
> 
> On Fri, 2017-12-22 at 15:18 -0800, Rodrigo Vivi wrote:
> > Since when it got introduced with commit '555e38d27317
> > ("drm/i915/cnl: DDI - PLL mapping")' the support for Port F
> > was wrong, because Port F bits are far from bits used
> > for A to E.
> > 
> > Since Port F is not used so far we don't need to propagate
> > Fixes back there.
> > 
> > Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> > Cc: Manasi Navare <manasi.d.navare at intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h | 12 ++++++++----
> >  1 file changed, 8 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 7b209f33a81e..12e3473168fe 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8668,10 +8668,14 @@ enum skl_power_gate {
> >   * CNL Clocks
> >   */
> >  #define DPCLKA_CFGCR0				_MMIO(0x6C200)
> > -#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port)+10))
> > -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << ((port)*2))
> > -#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port)*2)
> > -#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port)*2))
> > +#define  DPCLKA_CFGCR0_DDI_CLK_OFF(port)	(1 << ((port) ==  PORT_F ? 23 : \
> > +						      (port)+10))
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(port)	(3 << ((port) == PORT_F ? 21 : \
> > +						      (port)*2))
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL_SHIFT(port)	((port) == PORT_F ? 21 : \
> > +						(port)*2)
> > +#define  DPCLKA_CFGCR0_DDI_CLK_SEL(pll, port)	((pll) << ((port) == PORT_F ? 21 : \
> > +							   (port)*2))
> 
> How about 
> _MASK(port) = (3 << _SHIFT(port))
> _SEL(pll, port) = ((pll) << _SHIFT(PORT)) ?
> 
> Keeps MASK and SEL definitions simpler in this specific case.

I just didn't want to disrupt the current style nor wanted to
define a new macro that is only used in one case. :/

But I will consider these options on the next version.

Thanks,
Rodrigo.

> 
> 
> 
> >  
> >  /* CNL PLL */
> >  #define DPLL0_ENABLE		0x46010