[Intel-gfx] [PATCH v5] drm/i915/scheduler: emulate a scheduler for guc

[Chris Wilson]

On Wed, Feb 01, 2017 at 01:15:49PM +0000, Tvrtko Ursulin wrote:
> 
> On 01/02/2017 12:46, Chris Wilson wrote:
> >If we set the context-switch bit too early (and process the
> >user-interrupt and the context-switch as two separate passes through the
> >tasklet), we encounter the error from before that the CSB register may
> >be undefined. Possibly not since the user interrupt should mean the ring
> >is powered up (and so the register restored from the power context, one
> >hopes!), but there is no reason for us to read back the registers until
> >we see the interrupt telling us they have been updated.
> >
> >Note sure the best way to write that for simplicity, so I kept the patch
> >clean.
> >
> >        if (!(iir & ((GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT) << test_shift)))
> >                return;
> >
> >        if (iir & (GT_CONTEXT_SWITCH_INTERRUPT << test_shift))
> >                set_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted);
> >
> >        tasklet_hi_schedule(&engine->irq_tasklet);
> >
> >        if (iir & (GT_RENDER_USER_INTERRUPT << test_shift))
> >                notify_ring(engine);
> >
> >add/remove: 0/0 grow/shrink: 0/1 up/down: 0/-85 (-85)
> >function                                     old     new   delta
> >gen8_gt_irq_handler                          756     671     -85
> >Total: Before=1093982, After=1093897, chg -0.01%
> >
> >Ok, gcc likes that a lot more.
> 
> What's this add/remove grow/shrink up/down business? Something from
> some standard tool?

That was ./scripts/bloat-o-meter

> Back to the topic - should we be concerned here that in execlist
> mode we might wake up the tasklet prematurely? If it manages to run
> and exit in the window between the user interrupt and the context
> interrupt it would just waste cycles. I can easily see ~150us
> between the two here. What do you think?

Been worrying, but it's been below the level of sensitivity whilst using
my bdw. If some person did have some superfine tools to probe
latency/throughput ;) and it highlighted this as a problem, I was thinking
that we would simply split the gen8/gen9 interrupt (GT?) handling.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre