[Intel-gfx] [PATCH v1½ 00/13] drm/i915/dp: link rate and lane count refactoring

[Pandiyan, Dhinakaran]

On Thu, 2017-01-26 at 21:44 +0200, Jani Nikula wrote:
> This is kind of version 1½ of [1], basically just rebased on current git

Looks like this version didn't make it into patchwork.

-DK

> (including Manasi's test automation patches) and a couple of more
> cleanups slammed on top.
> 
> BR,
> Jani.
> 
> 
> [1] http://mid.mail-archive.com/cover.1485015599.git.jani.nikula@intel.com
> 
> 
> Jani Nikula (13):
>   drm/i915/dp: use known correct array size in rate_to_index
>   drm/i915/dp: return errors from rate_to_index()
>   drm/i915/dp: rename rate_to_index() to intel_dp_find_rate() and reuse
>   drm/i915/dp: cache source rates at init
>   drm/i915/dp: generate and cache sink rate array for all DP, not just
>     eDP 1.4
>   drm/i915/dp: use the sink rates array for max sink rates
>   drm/i915/dp: cache common rates with sink rates
>   drm/i915/dp: do not limit rate seek when not needed
>   drm/i915/dp: don't call the link parameters sink parameters
>   drm/i915/dp: add functions for max common link rate and lane count
>   drm/i915/mst: use max link not sink lane count
>   drm/i915/dp: localize link rate index variable more
>   drm/i915/dp: use readb and writeb calls for single byte DPCD access
> 
>  drivers/gpu/drm/i915/intel_dp.c               | 275 ++++++++++++++------------
>  drivers/gpu/drm/i915/intel_dp_link_training.c |   3 +-
>  drivers/gpu/drm/i915/intel_dp_mst.c           |   4 +-
>  drivers/gpu/drm/i915/intel_drv.h              |  19 +-
>  4 files changed, 166 insertions(+), 135 deletions(-)
>