[Intel-gfx] [PATCH 00/11] drm/msm: A5XX preemption

[Daniel Stone]

Hi,

On 6 February 2017 at 17:59, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Mon, Feb 06, 2017 at 10:39:28AM -0700, Jordan Crouse wrote:
>> This initial series implements 4 ringbuffers to give sufficient coverage for the
>> range of priority levels requested by the GLES and compute extensions. The
>> targeted ringbuffer is specified in the command submission flags. The default
>> ring is 0 (lowest priority).
>
> Link to userspace part that implements these extensions? Also which
> gles/compute extensions are you talking about? Asking not just because of
> the open source userspace requirement, but also because we want to
> upstream a scheduler on the i915 side. Getting alignment on that across
> drm drivers would be sweet.

Assuming he meant EGL rather than GLES, this is the usual one:
https://www.khronos.org/registry/EGL/extensions/IMG/EGL_IMG_context_priority.txt

Cheers,
Daniel