[Intel-gfx] [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for GLK

[Chauhan, Madhav]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Wednesday, February 8, 2017 8:24 PM
> To: Chauhan, Madhav <madhav.chauhan at intel.com>; intel-
> gfx at lists.freedesktop.org
> Cc: Shankar, Uma <uma.shankar at intel.com>; Mukherjee, Indranil
> <indranil.mukherjee at intel.com>; Kamath, Sunil <sunil.kamath at intel.com>;
> Saarinen, Jani <jani.saarinen at intel.com>; Conselvan De Oliveira, Ander
> <ander.conselvan.de.oliveira at intel.com>; Deepak M
> <m.deepak at intel.com>; Chauhan, Madhav <madhav.chauhan at intel.com>
> Subject: Re: [GLK MIPI DSI V4 1/8] drm/i915/glk: Program dphy param reg for
> GLK
> 
> On Tue, 07 Feb 2017, Madhav Chauhan <madhav.chauhan at intel.com>
> wrote:
> > From: Deepak M <m.deepak at intel.com>
> >
> > For GEMINILAKE, dphy param reg values are programmed in terms of HS
> > byte clock count while for older platforms in terms of HS ddr clk
> > count.
> >
> > v2: Added comments to clarify ddr clock count calculation
> >
> > Signed-off-by: Deepak M <m.deepak at intel.com>
> > Signed-off-by: Madhav Chauhan <madhav.chauhan at intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 45
> > ++++++++++++++++++++----------
> >  1 file changed, 31 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > index 8f683b8..b3c495f 100644
> > --- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > +++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
> > @@ -674,11 +674,6 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> >  		break;
> >  	}
> >
> > -	/*
> > -	 * ui(s) = 1/f [f in hz]
> > -	 * ui(ns) = 10^9 / (f*10^6) [f in Mhz] -> 10^3/f(Mhz)
> > -	 */
> > -
> >  	/* in Kbps */
> >  	ui_num = NS_KHZ_RATIO;
> >  	ui_den = bitrate;
> > @@ -692,19 +687,32 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> >  	 */
> >  	intel_dsi->lp_byte_clk = DIV_ROUND_UP(tlpx_ns * ui_den, 8 *
> ui_num);
> >
> > -	/* count values in UI = (ns value) * (bitrate / (2 * 10^6))
> > +	/* DDR clock period = 2 * UI
> > +	 * UI(sec) = 1/(bitrate * 10^3) (bitrate is in KHZ)
> > +	 * UI(nsec) = 10^6 / bitrate
> > +	 * DDR clock period (nsec) = 2 * UI = (2 * 10^6)/ bitrate
> > +	 * DDR clock count  = ns_value / DDR clock period
> >  	 *
> > -	 * Since txddrclkhs_i is 2xUI, all the count values programmed in
> > -	 * DPHY param register are divided by 2
> > +	 * For GEMINILAKE dphy_param_reg will be programmed in terms of
> > +	 * HS byte clock count for other platform in HS ddr clock count
> 
> Please add something like,
> 
> 	int mul = IS_GEMINILAKE(dev_priv) ? 8 : 2;
> 
> and use ui_num * mul instead of spreading IS_GEMINILAKE() check
> everywhere.

Correct, that's better way. Will include this in next series.

> 
> BR,
> Jani.
> 
> 
> >  	 *
> >  	 * prepare count
> >  	 */
> >  	ths_prepare_ns = max(mipi_config->ths_prepare,
> >  			     mipi_config->tclk_prepare);
> > -	prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den, ui_num *
> 2);
> > +	if (IS_GEMINILAKE(dev_priv))
> > +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 8);
> > +	else
> > +		prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * ui_den,
> ui_num * 2);
> >
> >  	/* exit zero count */
> > -	exit_zero_cnt = DIV_ROUND_UP(
> > +	if (IS_GEMINILAKE(dev_priv))
> > +		exit_zero_cnt = DIV_ROUND_UP(
> > +				(ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> > +				ui_num * 8
> > +				);
> > +	else
> > +		exit_zero_cnt = DIV_ROUND_UP(
> >  				(ths_prepare_hszero - ths_prepare_ns) *
> ui_den,
> >  				ui_num * 2
> >  				);
> > @@ -719,13 +727,22 @@ struct drm_panel *vbt_panel_init(struct intel_dsi
> *intel_dsi, u16 panel_id)
> >  		exit_zero_cnt += 1;
> >
> >  	/* clk zero count */
> > -	clk_zero_cnt = DIV_ROUND_UP(
> > -			(tclk_prepare_clkzero -	ths_prepare_ns)
> > -			* ui_den, 2 * ui_num);
> > +	if (IS_GEMINILAKE(dev_priv))
> > +		clk_zero_cnt = DIV_ROUND_UP(
> > +				(tclk_prepare_clkzero -	ths_prepare_ns)
> > +				* ui_den, 8 * ui_num);
> > +	else
> > +		clk_zero_cnt = DIV_ROUND_UP(
> > +				(tclk_prepare_clkzero -	ths_prepare_ns)
> > +				* ui_den, 2 * ui_num);
> >
> >  	/* trail count */
> >  	tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
> > -	trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 * ui_num);
> > +
> > +	if (IS_GEMINILAKE(dev_priv))
> > +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 8 *
> ui_num);
> > +	else
> > +		trail_cnt = DIV_ROUND_UP(tclk_trail_ns * ui_den, 2 *
> ui_num);
> >
> >  	if (prepare_cnt > PREPARE_CNT_MAX ||
> >  		exit_zero_cnt > EXIT_ZERO_CNT_MAX ||
> 
> --
> Jani Nikula, Intel Open Source Technology Center