[Intel-gfx] [PATCH v3] drm/i915: Make power domain masks 64 bit long
Ander Conselvan De Oliveira
conselvan2 at gmail.com
Thu Feb 9 09:32:51 UTC 2017
On Thu, 2017-02-09 at 11:31 +0200, Ander Conselvan de Oliveira wrote:
> There are currently 30 power domains, which puts us pretty close to the
> limit with 32 bit masks. Prepare for the future and increase the limit
> to 64 bit.
>
> v2: Rebase
> v3: s/unsigned long long/u64/ (Joonas)
> Allow the 64th bit of the mask to be used. (Joonas)
63rd.
>
> Cc: Jani Nikula <jani.nikula at linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Ville Syrjälä <ville.syrjala at linux.intel.com>
> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira at intel.
> com>
> Reviewed-by: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 4 +-
> drivers/gpu/drm/i915/intel_display.c | 34 +--
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 378 ++++++++++++++++---------------
> -
> 4 files changed, 209 insertions(+), 209 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 58bb5ca..ceb7699 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -494,7 +494,7 @@ struct i915_hotplug {
>
> #define for_each_power_domain(domain, mask) \
> for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
> - for_each_if ((1 << (domain)) & (mask))
> + for_each_if (BIT_ULL(domain) & (mask))
>
> struct drm_i915_private;
> struct i915_mm_struct;
> @@ -1405,7 +1405,7 @@ struct i915_power_well {
> int count;
> /* cached hw enabled state */
> bool hw_enabled;
> - unsigned long domains;
> + u64 domains;
> /* unique identifier for this power well */
> unsigned long id;
> /*
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index f6259c9..ab78df9 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5666,15 +5666,15 @@ intel_display_port_aux_power_domain(struct
> intel_encoder *intel_encoder)
> }
> }
>
> -static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
> - struct intel_crtc_state
> *crtc_state)
> +static u64 get_crtc_power_domains(struct drm_crtc *crtc,
> + struct intel_crtc_state *crtc_state)
> {
> struct drm_device *dev = crtc->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_encoder *encoder;
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum pipe pipe = intel_crtc->pipe;
> - unsigned long mask;
> + u64 mask;
> enum transcoder transcoder = crtc_state->cpu_transcoder;
>
> if (!crtc_state->base.active)
> @@ -5684,19 +5684,19 @@ static unsigned long get_crtc_power_domains(struct
> drm_crtc *crtc,
> mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
> if (crtc_state->pch_pfit.enabled ||
> crtc_state->pch_pfit.force_thru)
> - mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
> + mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
>
> drm_for_each_encoder_mask(encoder, dev, crtc_state-
> >base.encoder_mask) {
> struct intel_encoder *intel_encoder =
> to_intel_encoder(encoder);
>
> - mask |= BIT(intel_display_port_power_domain(intel_encoder));
> + mask |=
> BIT_ULL(intel_display_port_power_domain(intel_encoder));
> }
>
> if (HAS_DDI(dev_priv) && crtc_state->has_audio)
> mask |= BIT(POWER_DOMAIN_AUDIO);
>
> if (crtc_state->shared_dpll)
> - mask |= BIT(POWER_DOMAIN_PLLS);
> + mask |= BIT_ULL(POWER_DOMAIN_PLLS);
>
> return mask;
> }
> @@ -5708,7 +5708,7 @@ modeset_get_crtc_power_domains(struct drm_crtc *crtc,
> struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> enum intel_display_power_domain domain;
> - unsigned long domains, new_domains, old_domains;
> + u64 domains, new_domains, old_domains;
>
> old_domains = intel_crtc->enabled_power_domains;
> intel_crtc->enabled_power_domains = new_domains =
> @@ -5723,7 +5723,7 @@ modeset_get_crtc_power_domains(struct drm_crtc *crtc,
> }
>
> static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
> - unsigned long domains)
> + u64 domains)
> {
> enum intel_display_power_domain domain;
>
> @@ -8992,7 +8992,7 @@ static void haswell_get_ddi_pll(struct drm_i915_private
> *dev_priv,
>
> static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
> struct intel_crtc_state *pipe_config,
> - unsigned long *power_domain_mask)
> + u64 *power_domain_mask)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -9034,7 +9034,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc
> *crtc,
> power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> return false;
> - *power_domain_mask |= BIT(power_domain);
> + *power_domain_mask |= BIT_ULL(power_domain);
>
> tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
>
> @@ -9043,7 +9043,7 @@ static bool hsw_get_transcoder_state(struct intel_crtc
> *crtc,
>
> static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
> struct intel_crtc_state
> *pipe_config,
> - unsigned long *power_domain_mask)
> + u64 *power_domain_mask)
> {
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -9061,7 +9061,7 @@ static bool bxt_get_dsi_transcoder_state(struct
> intel_crtc *crtc,
> power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
> if (!intel_display_power_get_if_enabled(dev_priv,
> power_domain))
> continue;
> - *power_domain_mask |= BIT(power_domain);
> + *power_domain_mask |= BIT_ULL(power_domain);
>
> /*
> * The PLL needs to be enabled with a valid divider
> @@ -9136,13 +9136,13 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> enum intel_display_power_domain power_domain;
> - unsigned long power_domain_mask;
> + u64 power_domain_mask;
> bool active;
>
> power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
> if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
> return false;
> - power_domain_mask = BIT(power_domain);
> + power_domain_mask = BIT_ULL(power_domain);
>
> pipe_config->shared_dpll = NULL;
>
> @@ -9176,7 +9176,7 @@ static bool haswell_get_pipe_config(struct intel_crtc
> *crtc,
>
> power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
> if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
> - power_domain_mask |= BIT(power_domain);
> + power_domain_mask |= BIT_ULL(power_domain);
> if (INTEL_GEN(dev_priv) >= 9)
> skylake_get_pfit_config(crtc, pipe_config);
> else
> @@ -12841,7 +12841,7 @@ static void intel_atomic_commit_tail(struct
> drm_atomic_state *state)
> struct drm_crtc *crtc;
> struct intel_crtc_state *intel_cstate;
> bool hw_check = intel_state->modeset;
> - unsigned long put_domains[I915_MAX_PIPES] = {};
> + u64 put_domains[I915_MAX_PIPES] = {};
> unsigned crtc_vblank_mask = 0;
> int i;
>
> @@ -15565,7 +15565,7 @@ intel_modeset_setup_hw_state(struct drm_device *dev)
> ilk_wm_get_hw_state(dev);
>
> for_each_intel_crtc(dev, crtc) {
> - unsigned long put_domains;
> + u64 put_domains;
>
> put_domains = modeset_get_crtc_power_domains(&crtc->base,
> crtc->config);
> if (WARN_ON(put_domains))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index efd1bba..cf0c77f 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -715,7 +715,7 @@ struct intel_crtc {
> bool active;
> bool lowfreq_avail;
> u8 plane_ids_mask;
> - unsigned long enabled_power_domains;
> + unsigned long long enabled_power_domains;
> struct intel_overlay *overlay;
> struct intel_flip_work *flip_work;
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 0f00a5a..8795679 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -210,7 +210,7 @@ bool __intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
>
> is_enabled = true;
>
> - for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
> + for_each_power_well_rev(i, power_well, BIT_ULL(domain),
> power_domains) {
> if (power_well->always_on)
> continue;
>
> @@ -385,124 +385,124 @@ static void hsw_set_power_well(struct drm_i915_private
> *dev_priv,
> }
>
> #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_AUX_D) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DDI_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT(POWER_DOMAIN_MODESET) | \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_GMBUS) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT(POWER_DOMAIN_MODESET) | \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_DDI_A_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_DDI_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_DDI_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> #define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT(POWER_DOMAIN_MODESET) | \
> - BIT(POWER_DOMAIN_AUX_A) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> {
> @@ -1251,7 +1251,7 @@ static void vlv_dpio_cmn_power_well_disable(struct
> drm_i915_private *dev_priv,
> vlv_set_power_well(dev_priv, power_well, false);
> }
>
> -#define POWER_DOMAIN_MASK (GENMASK(POWER_DOMAIN_NUM - 1, 0))
> +#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
>
> static struct i915_power_well *lookup_power_well(struct drm_i915_private
> *dev_priv,
> int power_well_id)
> @@ -1697,7 +1697,7 @@ __intel_display_power_get_domain(struct drm_i915_private
> *dev_priv,
> struct i915_power_well *power_well;
> int i;
>
> - for_each_power_well(i, power_well, BIT(domain), power_domains)
> + for_each_power_well(i, power_well, BIT_ULL(domain), power_domains)
> intel_power_well_get(dev_priv, power_well);
>
> power_domains->domain_use_count[domain]++;
> @@ -1792,7 +1792,7 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> intel_display_power_domain_str(domain));
> power_domains->domain_use_count[domain]--;
>
> - for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
> + for_each_power_well_rev(i, power_well, BIT_ULL(domain),
> power_domains)
> intel_power_well_put(dev_priv, power_well);
>
> mutex_unlock(&power_domains->lock);
> @@ -1801,117 +1801,117 @@ void intel_display_power_put(struct drm_i915_private
> *dev_priv,
> }
>
> #define HSW_DISPLAY_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define BDW_DISPLAY_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DISPLAY_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_A) | \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DSI) | \
> - BIT(POWER_DOMAIN_PORT_CRT) | \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_GMBUS) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_CRT) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define CHV_DISPLAY_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PIPE_A) | \
> - BIT(POWER_DOMAIN_PIPE_B) | \
> - BIT(POWER_DOMAIN_PIPE_C) | \
> - BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DSI) | \
> - BIT(POWER_DOMAIN_VGA) | \
> - BIT(POWER_DOMAIN_AUDIO) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_AUX_D) | \
> - BIT(POWER_DOMAIN_GMBUS) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT(POWER_DOMAIN_AUX_B) | \
> - BIT(POWER_DOMAIN_AUX_C) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> - BIT(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT(POWER_DOMAIN_AUX_D) | \
> - BIT(POWER_DOMAIN_INIT))
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
>
> static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_always_on_power_well_noop,
> @@ -2388,7 +2388,7 @@ int intel_power_domains_init(struct drm_i915_private
> *dev_priv)
> dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
> i915.enable_dc);
>
> - BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
> + BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
>
> mutex_init(&power_domains->lock);
>
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