[Intel-gfx] [PATCH 0/6] Fix Geminilake DDI power well enable timeouts

[Ander Conselvan de Oliveira]

Geminilake's DDI IO power wells are peculiar in that they can't be
enabled without a DPLL running. This leads to enable timeouts in
different places during the init and modeset sequence. This patch
series attempts to fix those.

I'm not particularly happy about adding 5 new power domains in the last
patch, but I couldn't come up with another way to enable the power well
only at the right moment.

Thanks,
Ander

Ander Conselvan de Oliveira (6):
  drm/i915: Store aux power domain in intel_dp
  drm/i915: Store encoder power domain in struct intel_encoder
  drm/i915/glk: Implement WaDDIIOTimeout
  drm/i915/glk: Don't enable DDI IO power domains during init
  drm/i915/glk: Don't attempt to sync DDI IO power well hw state
  drm/i915: Only enable DDI IO power domains after enabling DPLL

 drivers/gpu/drm/i915/i915_drv.h         | 11 ++++
 drivers/gpu/drm/i915/i915_reg.h         |  5 ++
 drivers/gpu/drm/i915/intel_crt.c        | 21 ++++----
 drivers/gpu/drm/i915/intel_ddi.c        | 64 +++++++++++++++++++---
 drivers/gpu/drm/i915/intel_display.c    | 93 +++++---------------------------
 drivers/gpu/drm/i915/intel_dp.c         | 69 ++++++++++--------------
 drivers/gpu/drm/i915/intel_dp_mst.c     |  1 +
 drivers/gpu/drm/i915/intel_drv.h        | 10 ++--
 drivers/gpu/drm/i915/intel_dsi.c        |  9 ++--
 drivers/gpu/drm/i915/intel_dvo.c        |  1 +
 drivers/gpu/drm/i915/intel_hdmi.c       |  8 +--
 drivers/gpu/drm/i915/intel_lvds.c       |  8 +--
 drivers/gpu/drm/i915/intel_pm.c         | 10 ++++
 drivers/gpu/drm/i915/intel_runtime_pm.c | 96 +++++++++++++++++++++------------
 drivers/gpu/drm/i915/intel_sdvo.c       |  1 +
 drivers/gpu/drm/i915/intel_tv.c         |  1 +
 16 files changed, 216 insertions(+), 192 deletions(-)

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2.9.3