[Intel-gfx] [PATCH] drm/i915: Move the irq_barrier for reset earlier into reset_prepare
Michel Thierry
michel.thierry at intel.com
Fri Feb 10 20:05:53 UTC 2017
On 10/02/17 10:52, Chris Wilson wrote:
> When updating the bookkeeping following the reset, we need the seqno to
> be coherent on the CPU prior to trusting its result for deciding whether
> any request is completed. We need the irq_barrier before we start making
> these decisions, i.e. in reset_prepare.
>
> References: https://bugs.freedesktop.org/show_bug.cgi?id=99733
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at intel.com>
> ---
> drivers/gpu/drm/i915/i915_gem.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
I havent seen the issue in the platforms I have, but makes sense. If you
need one,
Reviewed-by: Michel Thierry <michel.thierry at intel.com>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index ed60d5881b40..3066f94da8f0 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -2677,6 +2677,9 @@ int i915_gem_reset_prepare(struct drm_i915_private *dev_priv)
> tasklet_disable(&engine->irq_tasklet);
> tasklet_kill(&engine->irq_tasklet);
>
> + if (engine->irq_seqno_barrier)
> + engine->irq_seqno_barrier(engine);
> +
> if (engine_stalled(engine)) {
> request = i915_gem_find_active_request(engine);
> if (request && request->fence.error == -EIO)
> @@ -2773,9 +2776,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine)
> {
> struct drm_i915_gem_request *request;
>
> - if (engine->irq_seqno_barrier)
> - engine->irq_seqno_barrier(engine);
> -
> request = i915_gem_find_active_request(engine);
> if (request && i915_gem_reset_request(request)) {
> DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n",
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
More information about the Intel-gfx
mailing list