[Intel-gfx] [PATCH] drm/i915: fix for WaDisableDopClockGating:bdw

[Robert Bragg]

On Wed, Feb 8, 2017 at 6:33 PM, Ville Syrjälä
<ville.syrjala at linux.intel.com> wrote:
> On Wed, Feb 08, 2017 at 06:10:31PM +0000, Robert Bragg wrote:
>> This workaround for BDW was incomplete as it also requires EUTC clock
>> gating to be disabled via UCGCTL1.
>
> IIRC that matches what I told Ben years ago when the w/a was first
> being added, and matches what I put in the CHV code when it still
> had this w/a. Presumably it still holds for BDW.

Poking into this I see now that 3e470eaaee5 which removes the
corresponding, pre-production, w/a for CHV removed a write to UCGCTL1
which is missing for BDW.

>
>>
>> Signed-off-by: Robert Bragg <robert at sixbynine.org>
>> ---
>>  drivers/gpu/drm/i915/intel_ringbuffer.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> index 49fa8006c6a2..fa1b400a79d0 100644
>> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
>> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
>> @@ -776,6 +776,7 @@ static int bdw_init_workarounds(struct intel_engine_cs *engine)
>>       /* WaDisableDopClockGating:bdw */
>>       WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2,
>>                         DOP_CLOCK_GATING_DISABLE);
>> +     WA_SET_BIT(GEN6_UCGCTL1, GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE);
>
> The UCGCTL registers aren't clobbered by GPU resets and whatnot, so
> we've historically kept them in the init_clock_gating() side.

Okey, I'll move here.

>
> Also it's not a masked register, and I'm not sure not all the bits
> default to 0, so you shouldn't perhaps just clobber them. Sadly the
> spec seems to have gone mad and no longer shows the default values
> for registers so I can't double check right now.

Ah, oops, I had a read modify write in i915-perf previously but yeah
this is no good. Moving this to broadwell_init_clock_gating() as a
read modify write is hopefully ok.

Thanks for the notes.
- Robert

>
>>
>>       WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
>>                         GEN8_SAMPLER_POWER_BYPASS_DIS);
>> --
>> 2.11.0
>>
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>
> --
> Ville Syrjälä
> Intel OTC