[Intel-gfx] [PATCH] drm/i915: Tidy workaround batch buffer emission

[Tvrtko Ursulin]

On 08/02/2017 14:44, Tvrtko Ursulin wrote:
> On 08/02/2017 13:20, Chris Wilson wrote:
>> On Wed, Feb 08, 2017 at 01:13:48PM +0000, Tvrtko Ursulin wrote:
>>> From: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
>>> -static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
>>> -                   struct i915_wa_ctx_bb *wa_ctx,
>>> -                   uint32_t *batch,
>>> -                   uint32_t *offset)
>>> +static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32
>>> *batch)
>>>  {
>>> -    uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
>>> -
>>> -    wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END);
>>> +    *batch++ = MI_BATCH_BUFFER_END;
>>>
>>> -    return wa_ctx_end(wa_ctx, *offset = index, 1);
>>> +    return batch;
>>>  }
>>
>> Transformation looks reasonable, but I'd like to omit this per-ctx bb
>> when empty.
>
> Don't know if that is possible. It is always programming the offset at
> the moment so documentation digging is required.

It is not clear to me from the spec if that would be OK. Looks like we 
have to have a MI_BB_END at the end of the perctx_bb so perhaps the hw 
executes sometimes the full batch (form indirect bb), and sometimes only 
the second part? So if we would omit the second one, we would need to 
put a BB_END on the first one (this would only apply in the gen9 case, 
gen8 already has an non-empty 2nd batch). Not sure that complication 
would be worth it.

Regards,

Tvrtko