[Intel-gfx] [PATCH] drm/i915/skl: Do not write the replay bit of the ring mode register for Gen 9

[Kelvin Gardiner]

The reply bit of the ring mode register is only valid on Gen 8.
Therefore do not write this for Gen 9.

Signed-off-by: Kelvin Gardiner <kelvin.gardiner at intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index ee431d3..fa15377 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1259,9 +1259,15 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
 	intel_engine_init_hangcheck(engine);
 
 	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
-	I915_WRITE(RING_MODE_GEN7(engine),
-		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
-		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
+	if (INTEL_GEN(dev_priv) >= 9)
+		I915_WRITE(RING_MODE_GEN7(engine),
+			_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+	else
+		I915_WRITE(RING_MODE_GEN7(engine),
+			_MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
+			_MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
+
 	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
 		   engine->status_page.ggtt_offset);
 	POSTING_READ(RING_HWS_PGA(engine->mmio_base));
-- 
1.9.1