[Intel-gfx] [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link

[Srinivas, Vidya]

> -----Original Message-----
> From: Nikula, Jani
> Sent: Thursday, February 16, 2017 8:56 PM
> To: Paauwe, Bob J <bob.j.paauwe at intel.com>; Srinivas, Vidya
> <vidya.srinivas at intel.com>
> Cc: intel-gfx at lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 8/9] drm/i915/bxt: Enable BXT DSI dual link
> 
> On Wed, 15 Feb 2017, Bob Paauwe <bob.j.paauwe at intel.com> wrote:
> > On Wed, 8 Feb 2017 16:20:57 +0530
> > Vidya Srinivas <vidya.srinivas at intel.com> wrote:
> >
> >> From: Uma Shankar <uma.shankar at intel.com>
> >>
> >> Enable support for BXT DSI dual link mode.
> >>
> >> Signed-off-by: Uma Shankar <uma.shankar at intel.com>
> >> Signed-off-by: Vidya Srinivas <vidya.srinivas at intel.com>
> >
> > Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com>
> 
> This doesn't apply because I've pushed
> 
> commit 6043801f937ada9c9ed9dfa3c6ce542a79643401
> Author: Deepak M <m.deepak at intel.com>
> Date:   Tue Feb 14 18:46:16 2017 +0530
> 
>     drm/i915: Set the Z inversion overlap field
> 
> Please update the patch, and in general, please send a new series of patches
> that do *not* depend on the drm_panel changes. We can get all of those
> merged first. We should try to make progress.
> 
> BR,
> Jani.

Thanks Jani. I will rebase and re-submit and also  to remove drm_panel
interface dependency, I am planning to create panel sequence callbacks
in intel_dsi structure itself. Is this approach okay?

Regards
Vidya

> 
> 
> >
> >> ---
> >>  drivers/gpu/drm/i915/i915_reg.h  |  5 +++++
> >> drivers/gpu/drm/i915/intel_dsi.c | 27 ++++++++++++++++++---------
> >>  2 files changed, 23 insertions(+), 9 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> >> b/drivers/gpu/drm/i915/i915_reg.h index 07b1a2d..3b2925c 100644
> >> --- a/drivers/gpu/drm/i915/i915_reg.h
> >> +++ b/drivers/gpu/drm/i915/i915_reg.h
> >> @@ -8425,6 +8425,7 @@ enum {
> >>  #define  LANE_CONFIGURATION_4LANE			(0 << 0)
> >>  #define  LANE_CONFIGURATION_DUAL_LINK_A			(1 <<
> 0)
> >>  #define  LANE_CONFIGURATION_DUAL_LINK_B			(2 <<
> 0)
> >> +#define  LANE_CONFIGURATION_DUAL_LINK_ENABLE		(1 <<
> 0)
> >>
> >>  #define _MIPIA_TEARING_CTRL			(VLV_DISPLAY_BASE
> + 0x61194)
> >>  #define _MIPIC_TEARING_CTRL			(VLV_DISPLAY_BASE
> + 0x61704)
> >> @@ -8758,6 +8759,10 @@ enum {
> >>  #define  READ_REQUEST_PRIORITY_HIGH			(3 << 3)
> >>  #define  RGB_FLIP_TO_BGR				(1 << 2)
> >>
> >> +/* BXT has dual link Z inversion overlap field */
> >> +#define  BXT_PIXEL_OVERLAP_CNT_MASK			(0xf << 10)
> >> +#define  BXT_PIXEL_OVERLAP_CNT_SHIFT			10
> >> +
> >>  #define  BXT_PIPE_SELECT_SHIFT				7
> >>  #define  BXT_PIPE_SELECT_MASK				(7 << 7)
> >>  #define  BXT_PIPE_SELECT(pipe)				((pipe) << 7)
> >> diff --git a/drivers/gpu/drm/i915/intel_dsi.c
> >> b/drivers/gpu/drm/i915/intel_dsi.c
> >> index 12aeee1..60ca0b9 100644
> >> --- a/drivers/gpu/drm/i915/intel_dsi.c
> >> +++ b/drivers/gpu/drm/i915/intel_dsi.c
> >> @@ -440,15 +440,24 @@ static void intel_dsi_port_enable(struct
> intel_encoder *encoder)
> >>  	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
> >>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
> >>  	enum port port;
> >> +	u32 temp;
> >>
> >>  	if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
> >> -		u32 temp;
> >> -
> >> -		temp = I915_READ(VLV_CHICKEN_3);
> >> -		temp &= ~PIXEL_OVERLAP_CNT_MASK |
> >> +		if (IS_BROXTON(dev_priv)) {
> >> +			for_each_dsi_port(port, intel_dsi->ports) {
> >> +				temp = I915_READ(MIPI_CTRL(port));
> >> +				temp &= ~BXT_PIXEL_OVERLAP_CNT_MASK
> |
> >>  					intel_dsi->pixel_overlap <<
> >> -					PIXEL_OVERLAP_CNT_SHIFT;
> >> -		I915_WRITE(VLV_CHICKEN_3, temp);
> >> +					BXT_PIXEL_OVERLAP_CNT_SHIFT;
> >> +				I915_WRITE(MIPI_CTRL(port), temp);
> >> +			}
> >> +		} else {
> >> +			temp = I915_READ(VLV_CHICKEN_3);
> >> +			temp &= ~PIXEL_OVERLAP_CNT_MASK |
> >> +				intel_dsi->pixel_overlap <<
> >> +				PIXEL_OVERLAP_CNT_SHIFT;
> >> +			I915_WRITE(VLV_CHICKEN_3, temp);
> >> +		}
> >>  	}
> >>
> >>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -464,12 +473,12
> @@
> >> static void intel_dsi_port_enable(struct intel_encoder *encoder)
> >>  		if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
> >>  			temp |= (intel_dsi->dual_link - 1)
> >>  						<<
> DUAL_LINK_MODE_SHIFT;
> >> -			if (IS_BROXTON(dev_priv))
> >> -				temp |=
> LANE_CONFIGURATION_DUAL_LINK_A;
> >> -			else
> >> +			if (IS_VALLEYVIEW(dev_priv))
> >>  				temp |= intel_crtc->pipe ?
> >>
> 	LANE_CONFIGURATION_DUAL_LINK_B :
> >>
> 	LANE_CONFIGURATION_DUAL_LINK_A;
> >> +			else if (IS_BROXTON(dev_priv))
> >> +				temp |=
> LANE_CONFIGURATION_DUAL_LINK_ENABLE;
> >>  		}
> >>  		/* assert ip_tg_enable signal */
> >>  		I915_WRITE(port_ctrl, temp | DPI_ENABLE);
> 
> --
> Jani Nikula, Intel Open Source Technology Center