[Intel-gfx] [PATCH v2] drm/i915/guc: fix mmio whitelist mmio_start offset and add reminder

[Michał Winiarski]

On Wed, Feb 22, 2017 at 05:19:27PM -0800, Daniele Ceraolo Spurio wrote:
> The mmio_start offset for the whitelist is the first FORCE_TO_NONPRIV
> register the GuC can use to restore the provided whitelist when an
> engine reset via GuC (which we still don't support) is triggered.
> 
> We're currently adding the mmio_base of the engine to the absolute
> address of the RCS version of the register, which results in the wrong
> offset. Fix it by using the definition we already have instead of
> re-defining it in the GuC FW header.
> 
> Also add a comment to avoid future issues with FORCE_TO_NONPRIV
> registers, which are also used by the workaround framework.
> 
> v2: improve comment (Michal), move comment about save/restore because it
>     is not related to the mmio_white_list field.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Michał Winiarski <michal.winiarski at intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko at intel.com>
> Cc: Arkadiusz Hiler <arkadiusz.hiler at intel.com>
> Cc: Oscar Mateo <oscar.mateo at intel.com>

Reviewed-by: Michał Winiarski <michal.winiarski at intel.com>

-Michał

> ---
>  drivers/gpu/drm/i915/i915_guc_submission.c | 11 +++++++++--
>  drivers/gpu/drm/i915/intel_guc_fwif.h      |  1 -
>  2 files changed, 9 insertions(+), 3 deletions(-)