[Intel-gfx] [PATCH 2/5] drm/i915: Remove redundant TLB invalidate on switching ppgtt

[Chris Wilson]

On Fri, Feb 24, 2017 at 11:47:56AM +0200, Mika Kuoppala wrote:
> Chris Wilson <chris at chris-wilson.co.uk> writes:
> 
> > We are required to reload the TLBs around ppgtt switches. However, we
> > already do an unconditional TLB invalidate before every batch and a flush
> > afterwards, so this condition is already satisfied without extra flushes
> > around the LRI instructions.
> >
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 17 -----------------
> >  1 file changed, 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 057239ab3f70..999f15455f48 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -1431,13 +1431,8 @@ static int hsw_mm_switch(struct i915_hw_ppgtt *ppgtt,
> >  {
> >  	struct intel_engine_cs *engine = req->engine;
> >  	u32 *cs;
> > -	int ret;
> >  
> >  	/* NB: TLBs must be flushed and invalidated before a switch */
> > -	ret = engine->emit_flush(req, EMIT_INVALIDATE | EMIT_FLUSH);
> 
> The pattern slightly changes as you dont get the flush on the first
> switch.
> 
> But what is there to flush on first switch anyways.

Those flushes onto the empty ring have always left me questioning my
sanity ;)
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre