[Intel-gfx] [PATCH v2] drm/i915/bdw: Do not write the replay bit of the ring mode register

[Daniele Ceraolo Spurio]

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

On 24/02/17 11:15, Kelvin Gardiner wrote:
> The replay bit of the ring mode register is not a valid bit for Gen8+. Do not
> write to this bit.
>
> Signed-off-by: Kelvin Gardiner <kelvin.gardiner at intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 1 -
>  1 file changed, 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 1c6c716..f9a8545 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1178,7 +1178,6 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
>
>  	I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
>  	I915_WRITE(RING_MODE_GEN7(engine),
> -		   _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) |
>  		   _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
>  	I915_WRITE(RING_HWS_PGA(engine->mmio_base),
>  		   engine->status_page.ggtt_offset);
>