[Intel-gfx] [PATCH resend 15/15] drm/i915/dsi: Skip delays for v3 VBTs in vid-mode

[Hans de Goede]

HI,

On 24-02-17 18:02, Bob Paauwe wrote:
> On Mon, 20 Feb 2017 15:08:45 +0100
> Hans de Goede <hdegoede at redhat.com> wrote:
>
>> For v3 VBTs in vid-mode the delays are part of the VBT sequences, so
>> we should not also delay ourselves otherwise we get double delays.
>>
>> Signed-off-by: Hans de Goede <hdegoede at redhat.com>
>> ---
>>  drivers/gpu/drm/i915/intel_dsi.c | 19 +++++++++++++++----
>>  1 file changed, 15 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
>> index a001e43..9e858c7 100644
>> --- a/drivers/gpu/drm/i915/intel_dsi.c
>> +++ b/drivers/gpu/drm/i915/intel_dsi.c
>> @@ -552,6 +552,17 @@ static void intel_dsi_prepare(struct intel_encoder *intel_encoder,
>>  			      struct intel_crtc_state *pipe_config);
>>  static void intel_dsi_unprepare(struct intel_encoder *encoder);
>>
>> +static void intel_dsi_msleep(struct intel_dsi *intel_dsi, int msec)
>> +{
>> +	struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
>> +
>> +	/* For v3 VBTs in vid-mode the delays are part of the VBT sequences */
>> +	if (is_vid_mode(intel_dsi) && dev_priv->vbt.dsi.seq_version >= 3)
>> +		return;
>> +
>> +	msleep(msec);
>> +}
>> +
>>  /*
>>   * Panel enable/disable sequences from the VBT spec.
>>   *
>> @@ -664,7 +675,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>>  	if (intel_dsi->gpio_panel)
>>  		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1);
>>  	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
>> -	msleep(intel_dsi->panel_on_delay);
>> +	intel_dsi_msleep(intel_dsi, intel_dsi->panel_on_delay);
>>
>>  	/* Deassert reset */
>>  	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
>> @@ -686,7 +697,7 @@ static void intel_dsi_pre_enable(struct intel_encoder *encoder,
>>  		msleep(20); /* XXX */
>>  		for_each_dsi_port(port, intel_dsi->ports)
>>  			dpi_send_cmd(intel_dsi, TURN_ON, false, port);
>> -		msleep(100);
>> +		intel_dsi_msleep(intel_dsi, 100);
>>
>>  		intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
>>
>> @@ -805,7 +816,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
>>  	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
>>
>>  	/* Power off, try both CRC pmic gpio and VBT */
>> -	msleep(intel_dsi->panel_off_delay);
>> +	intel_dsi_msleep(intel_dsi, intel_dsi->panel_off_delay);
>>  	intel_dsi_exec_vbt_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
>>  	if (intel_dsi->gpio_panel)
>>  		gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0);
>> @@ -814,7 +825,7 @@ static void intel_dsi_post_disable(struct intel_encoder *encoder,
>>  	 * FIXME As we do with eDP, just make a note of the time here
>>  	 * and perform the wait before the next panel power on.
>>  	 */
>
> Should this comment be updated now?

It is still valid for non-vidmode and v2 VBT panels, so I think it can
be left as is.

Regards,

Hans




>
> Otherwise
> Reviewed-by: Bob Paauwe <bob.j.paauwe at intel.com>
>
>> -	msleep(intel_dsi->panel_pwr_cycle_delay);
>> +	intel_dsi_msleep(intel_dsi, intel_dsi->panel_pwr_cycle_delay);
>>  }
>>
>>  static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
>
>
>