[Intel-gfx] [PATCH 07/10] drm/i915/psr: set PSR_MASK bits for deep sleep

[Ilia Mirkin]

On Mon, Jan 2, 2017 at 6:31 AM, vathsala nagaraju
<vathsala.nagaraju at intel.com> wrote:
> Program EDP_PSR_DEBUG_CTL (PSR_MASK) to enable system
> to go to deep sleep while in psr2.PSR2_STATUS bit 31:28
> should report value 8 , if system enters deep sleep state.
>
> Also, EDP_FRAMES_BEFORE_SU_ENTRY is set 1 , if not set,
> flickering is observed on psr2 panel.
>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Jim Bride <jim.bride at linux.intel.com>
> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju at intel.com>
> Signed-off-by: Patil Deepti <deepti.patil at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  |  7 +++++++
>  drivers/gpu/drm/i915/intel_dp.c  |  1 -
>  drivers/gpu/drm/i915/intel_psr.c | 29 ++++++++++++++++++++---------
>  3 files changed, 27 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 5ca506a..0cbe564 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3600,6 +3600,12 @@ enum {
>  #define   EDP_PSR_DEBUG_MASK_LPSP      (1<<27)
>  #define   EDP_PSR_DEBUG_MASK_MEMUP     (1<<26)
>  #define   EDP_PSR_DEBUG_MASK_HPD       (1<<25)
> +#define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1<<28)
> +#define   EDP_PSR_DEBUG_MASK_LPSP              (1<<27)
> +#define   EDP_PSR_DEBUG_MASK_MEMUP             (1<<26)
> +#define   EDP_PSR_DEBUG_MASK_HPD               (1<<25)

Looks like you're defining the above 3 (maybe 4 - not enough context)
a second time.

  -ilia