[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

[Rodrigo Vivi]

Please don't forget about the bit 11 for KBL. In a separated patch.

This patch is correct and count with my rv-b, but I believe the best place for this is 
on intel_psr_enable, right after setup_vsc.

On Mon, Jan 02, 2017 at 05:00:59PM +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15
> must be programmed.
> Enable bit 12 for programmable header packet.
> Enable bit 15 for Y cordinate support.
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Jim Bride <jim.bride at linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju at intel.com>
> Signed-off-by: Patil Deepti <deepti.patil at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 7 +++++++
>  drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..5ca506a 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,13 @@ enum {
>  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>  
> +#define CHICKEN_TRANS_A         0x420c0
> +#define CHICKEN_TRANS_B         0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define TRANS_EDP              3
> +#define CHICKEN_TRANS_BIT12    (1<<12)
> +#define CHICKEN_TRANS_BIT15    (1<<15)
> +
>  #define DISP_ARB_CTL	_MMIO(0x45000)
>  #define  DISP_FBC_MEMORY_WAKE		(1<<31)
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 494e4b2..2e75ef6 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -332,6 +332,7 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	 */
>  	uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
>  	uint32_t val = EDP_PSR_ENABLE;
> +	uint32_t chicken_trans = 0;
>  
>  	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
>  
> @@ -349,6 +350,12 @@ static void hsw_enable_source_psr2(struct intel_dp *intel_dp)
>  	else
>  		val |= EDP_PSR2_TP2_TIME_50;
>  
> +	/* Set CHICKEN_TRANS_BIT15 if Y coordinate is supported */
> +	if (dev_priv->psr.y_cord_support)
> +		chicken_trans = CHICKEN_TRANS_BIT15;
> +	/* Set CHICKEN_TRANS_BIT12 for programable header */
> +	chicken_trans = chicken_trans | CHICKEN_TRANS_BIT12;
> +	I915_WRITE(CHICKEN_TRANS(TRANS_EDP), chicken_trans);
>  	I915_WRITE(EDP_PSR2_CTL, val);
>  }
>  
> -- 
> 1.9.1
>