[Intel-gfx] [PATCH 07/10] drm/i915: Align GGTT sizes to a fence tile row

[Chris Wilson]

On Mon, Jan 09, 2017 at 03:21:43PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +0000, Chris Wilson wrote:
> > Ensure the view occupies the full tile row so that reads/writes into the
> > VMA do not escape (via fenced detiling) into neighbouring objects - we
> > will pad the object with scratch pages to satisfy the fence. This
> > applies the lazy-tiling we employed on gen2/3 to gen4+.
> > 
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> 
> <SNIP>
> 
> >  u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv,
> > -			   u64 size, int tiling_mode)
> > +			   u64 size, int tiling_mode, unsigned int stride)
> >  {
> >  	u64 ggtt_size;
> >  
> > -	GEM_BUG_ON(size == 0);
> > +	GEM_BUG_ON(!size);
> >  
> > -	if (INTEL_GEN(dev_priv) >= 4 ||
> > -	    tiling_mode == I915_TILING_NONE)
> > +	if (tiling_mode == I915_TILING_NONE)
> >  		return size;
> >  
> > +	GEM_BUG_ON(!stride);
> > +
> > +	if (INTEL_GEN(dev_priv) >= 4) {
> > +		stride *= tiling_mode == I915_TILING_Y ? 32 : 8;
> 
> (Split from tile_row_pages and) use tile_row_size() here? I915_TILING_Y
> ? 32 : 8 should really be in one place.

But, it's repeated so often, it must be good! :)
 
> > +		GEM_BUG_ON(stride & 4095);
> 
> ~PAGE_MASK? Or even (4096 - 1) is better, so that it gets caught when
> converting to non-hardcoded page sizes. CC'ing Matt.

I've a patch for later (after this one) to do conversions to
PAGE_SIZE, I915_GTT_PAGE_SIZE, I915_GTT_MIN_ALIGNMENT and use
IS_ALIGNED().
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre