[Intel-gfx] [PATCH 01/10] drm/i915: Pack the partial view size and offset into a single u64
joonas.lahtinen at linux.intel.com
Mon Jan 9 14:13:50 UTC 2017
On pe, 2017-01-06 at 15:25 +0000, Chris Wilson wrote:
> Since the partial offset must be page aligned, we can use those low 12
> bits to encode the size of the partial view (which then cannot be larger
> than 8MiB in pages).
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
Lets just not, it makes the code unnecessarily hard to read (and for
$DEITY's sake, I wrote the initial partial code). I think we have
enough bugs in the MMIO parts that have to deal with packed registers.
Open Source Technology Center
More information about the Intel-gfx