[Intel-gfx] [PATCH 09/10] drm/i915: Store required fence size/alignment for GGTT vma
chris at chris-wilson.co.uk
Mon Jan 9 14:14:02 UTC 2017
On Mon, Jan 09, 2017 at 04:05:01PM +0200, Joonas Lahtinen wrote:
> On pe, 2017-01-06 at 15:25 +0000, Chris Wilson wrote:
> Commit message missing.
> > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> > @@ -3360,11 +3360,10 @@ int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
> > int i915_gem_open(struct drm_device *dev, struct drm_file *file);
> > void i915_gem_release(struct drm_device *dev, struct drm_file *file);
> > -u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u64 size,
> > +u32 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, u32 size,
> We still seem to have some type bouncing going on.
Since we have restricted ggtt to only be u32, I'm correcting the
interfaces as I go.
> > @@ -3577,7 +3573,7 @@ i915_gem_object_unpin_from_display_plane(struct i915_vma *vma)
> > return;
> > if (--vma->obj->pin_display == 0)
> > - vma->display_alignment = 0;
> > + vma->display_alignment = 4096;
> Is there a case when the max() become zero? Do we have Bugzilla or is
> this just preventive action.
It's a change to accommodate this patch to simplify the alignment
compuation as a series of max().
Chris Wilson, Intel Open Source Technology Centre
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