[Intel-gfx] DP compliance failure due to dithering for 18bpp video pattern

[Jani Nikula]

On Tue, 10 Jan 2017, Manasi Navare <manasi.d.navare at intel.com> wrote:
> Hi All,
>
> We are seeing CRC check failures in some of the 18bpp video pattern
> DP Compliance tests causing the tests to fail. On further investigation, it is
> rootcaused to dithering that the i915 driver enables in case of 18bpp pipe
> configuration that messes up the CRC and causes the test to fail.

The CTS spec actually accounts for CRC failures caused by dithering and
color space conversions. See section 3.2.1. However, it would be
preferrable to be able to automate this.

> Some of the approaches that can solve this problem are:
> 1.  Add a new method in intel_dp.c to request the compliance test state.
> Call this new method in intel_display.c to not enable dithering during a
> compliance test. Issue with this is it makes the general portion of the driver
> compliance aware.
>
> 2.  Move the dithering enable to compute_config methods in all encoder source
> files. Issue: Lot of duplicate code and DP is the only encoder that uses 18bpc.
>
> 3.  Disable dithering at all times in the driver. However this can cause image
> quality issue with 8bpc plane and 6 bit pipe.
>
> Any suggestions on which approach can be implemented in order to pass
> compliance?

I can't find any mention in the specs that we couldn't enable/disable
dithering on the fly. It's PIPE_MISC for BDW+ and PIPE_CONF for the
rest. So I'm wondering about doing...

4. Disable dithering at intel_dp_sink_crc_start() and enable it again
   (according to config->dither) at intel_dp_sink_crc_stop(). It's
   similar to the hsw_disable_ips() and hsw_enable_ips() calls, but
   would have to cover more platforms.

Ville, thoughts on changing dithering on the fly?

BR,
Jani.



>
> Regards
> Manasi
>
>
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-- 
Jani Nikula, Intel Open Source Technology Center