[Intel-gfx] [PATCH 06/10] drm/i915/psr: set CHICKEN_TRANS for psr2

[Vivi, Rodrigo]

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

On Fri, 2017-01-13 at 00:31 +0530, vathsala nagaraju wrote:
> As per bpsec, CHICKEN_TRANS_EDP bit 12 ,15 must be programmed in
> psr2 enable sequence.
> bit 12 : Program Transcoder EDP VSC DIP header with a valid setting for
>         PSR2 and Set CHICKEN_TRANS_EDP(0x420cc) bit 12 for programmable
>         header packet.
> bit 15 : Set CHICKEN_TRANS_EDP(0x420cc) bit 15 if Y coordinate is supported
> 
> v2: (Rodrigo)
> - move CHICKEN_TRANS_EDP bit set logic right after setup_vsc
> 
> v3:(Rodrigo)
> - initialize chicken_trans to CHICKEN_TRANS_BIT12 instead of 0
> 
> v4:(chris wilson)
> - use BIT(12), remove CHICKEN_TRANS_BIT12
> - remove unnecessary comments
> - update commit message
> 
> v5:
> - rename bit 12 PSR2_VSC_ENABLE_PROG_HEADER
> - rename bit 15 PSR2_ADD_VERTICAL_LINE_COUNT
> 
> v6:(Rodrigo)
> - remove TRANS_EDP=3, use cpu_transcoder
> 
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Cc: Jim Bride <jim.bride at linux.intel.com>
> Signed-off-by: vathsala nagaraju <vathsala.nagaraju at intel.com>
> Signed-off-by: Patil Deepti <deepti.patil at intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 6 ++++++
>  drivers/gpu/drm/i915/intel_psr.c | 7 +++++++
>  2 files changed, 13 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 7830e6e..c9c1ccd 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -6449,6 +6449,12 @@ enum {
>  #define  BDW_DPRS_MASK_VBLANK_SRD	(1 << 0)
>  #define CHICKEN_PIPESL_1(pipe) _MMIO_PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
>  
> +#define CHICKEN_TRANS_A         0x420c0
> +#define CHICKEN_TRANS_B         0x420c4
> +#define CHICKEN_TRANS(trans) _MMIO_TRANS(trans, CHICKEN_TRANS_A, CHICKEN_TRANS_B)
> +#define PSR2_VSC_ENABLE_PROG_HEADER    (1<<12)
> +#define PSR2_ADD_VERTICAL_LINE_COUNT   (1<<15)
> +
>  #define DISP_ARB_CTL	_MMIO(0x45000)
>  #define  DISP_FBC_MEMORY_WAKE		(1<<31)
>  #define  DISP_TILE_SURFACE_SWIZZLING	(1<<13)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index 36c4045..935402e 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -480,6 +480,9 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
>  	struct drm_device *dev = intel_dig_port->base.base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
> +	enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
> +	u32 chicken;
>  
>  	if (!HAS_PSR(dev_priv)) {
>  		DRM_DEBUG_KMS("PSR not supported on this platform\n");
> @@ -505,6 +508,10 @@ void intel_psr_enable(struct intel_dp *intel_dp)
>  	if (HAS_DDI(dev_priv)) {
>  		if (dev_priv->psr.psr2_support) {
>  			skl_psr_setup_su_vsc(intel_dp);
> +			chicken = PSR2_VSC_ENABLE_PROG_HEADER;
> +			if (dev_priv->psr.y_cord_support)
> +				chicken |= PSR2_ADD_VERTICAL_LINE_COUNT;
> +			I915_WRITE(CHICKEN_TRANS(cpu_transcoder), chicken);
>  		} else {
>  			/* set up vsc header for psr1 */
>  			hsw_psr_setup_vsc(intel_dp);