[Intel-gfx] [PATCH] drm/i915: Re-enable preallocated top level PDPs support

Chris Wilson chris at chris-wilson.co.uk
Thu Jan 19 12:09:24 UTC 2017


On Thu, Jan 19, 2017 at 12:52:39PM +0100, Michał Winiarski wrote:
> On Tue, Jan 17, 2017 at 10:06:12PM +0800, Zhi Wang wrote:
> > After PPGTT page table is able to be shrinken, the preallocated PDPs and
> > PDE pages can be freed even they are preallocated under 3-level PPGTT
> > mode. This patch re-enables preallocated top level PDPs and PDE pages
> > like before.
> > 
> > Cc: Michał Winiarski <michal.winiarski at intel.com>
> > Cc: Michel Thierry <michel.thierry at intel.com>
> > Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> > Cc: Chris Wilson <chris at chris-wilson.co.uk>
> > Cc: Zhenyu Wang <zhenyuw at linux.intel.com>
> > Cc: Zhiyuan Lv <zhiyuan.lv at intel.com>
> > Signed-off-by: Zhi Wang <zhi.a.wang at intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_gem_gtt.c | 10 +++++++++-
> >  drivers/gpu/drm/i915/i915_gem_gtt.h |  1 +
> >  drivers/gpu/drm/i915/intel_lrc.c    |  2 +-
> >  3 files changed, 11 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > index 8aca11f..f0e1992 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> > @@ -793,12 +793,18 @@ static bool gen8_ppgtt_clear_pdp(struct i915_address_space *vm,
> >  	struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vm);
> >  	struct i915_page_directory *pd;
> >  	uint64_t pdpe;
> > +	bool pd_is_empty;
> >  
> >  	gen8_for_each_pdpe(pd, pdp, start, length, pdpe) {
> >  		if (WARN_ON(!pdp->page_directory[pdpe]))
> >  			break;
> >  
> > -		if (gen8_ppgtt_clear_pd(vm, pd, start, length)) {
> > +		pd_is_empty = gen8_ppgtt_clear_pd(vm, pd, start, length);
> 
> Why the extra pd_is_empty variable?
> Just adding if (preallocate) continue; here is more readable imho.
> 
> We should also assert that we're not in 4-level paging mode when shrinking is
> skipped.

I've restructured this so that we only shrink from clear_range_4lvl.
Having written the tests to exercise your code and put it to use.

Michał can you look at the ppgtt selftests can see if you can think of
any other way we might be able to exercise the alloc/insert/clear?
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre


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