[Intel-gfx] [PATCH v3 00/14] drm/i915: Introduce intel_cdclk_state (v3)

[Ander Conselvan De Oliveira]

On Fri, 2017-01-20 at 20:21 +0200, ville.syrjala at linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala at linux.intel.com>
> 
> Here's the latest version of my cdclk state work. I tried to accomodate
> most of the review feedback, although there were some comments which
> I think are better left for a followup work. Mainly about renaming some
> functions and whatnot to make more sense, and probably adjusting how
> we do the state swap.

Yeah, I didn't intend to block these on those comments. I reviewed the first
patch and skimmed through the others and didn't notice anything wrong with them.

Ander

> 
> On that last point, I left that 'hw' state under dev_priv->cdclk. I think
> we should be able to get rid of that if we pass the old cdclk state down
> to the code that actually programs the cdlck (since that code wants to
> compare the new and current states to see which parts of the programming
> are needed).
> 
> Another thing I realized recently is that we have no protection against
> gmbus or aux vs. cdclk reprogramming. On some platforms/ports gmbus and/or
> aux is clock by cdclk, so I think we need to add some protection. Fortunately
> both gmbus and aux have their own low level mutexes so I think we should be
> able to just grab those around the reprogramming part. Although for this
> we might have to keep the 'hw' cdclk state as we'd need to make sure the
> gmbus/aux code programs the dividers based on the actual hardware state.
> 
> So, there's still some work left, but I think we should be able to move
> this forward and hopefully unblock some *future* stuff.
> 
> Entire series available here:
> git://github.com/vsyrjala/linux.git cdclk_state_4
> 
> Ville Syrjälä (14):
>   drm/i915: Store the pipe pixel rate in the crtc state
>   drm/i915: Nuke intel_mode_max_pixclk()
>   drm/i915: s/get_display_clock_speed/get_cdclk/
>   drm/i915: Clean up the .get_cdclk() assignment if ladder
>   drm/i915: Move most cdclk/rawclk related code to intel_cdclk.c
>   drm/i915: Pass computed vco to bxt_set_cdclk()
>   drm/i915: Start moving the cdclk stuff into a distinct state structure
>   drm/i915: Track full cdclk state for the logical and actual cdclk
>     frequencies
>   drm/i915: Pass dev_priv to remainder of the cdclk functions
>   drm/i915: Pass the cdclk state to the set_cdclk() functions
>   drm/i915: Move PFI credit reprogramming into vlv/chv_set_cdclk()
>   drm/i915: Nuke the VLV/CHV PFI programming power domain workaround
>   drm/i915: Replace the .modeset_commit_cdclk() hook with a more direct
>     .set_cdclk() hook
>   drm/i915: Move ilk_pipe_pixel_rate() to intel_display.c
> 
>  Documentation/gpu/i915.rst              |    9 +
>  drivers/gpu/drm/i915/Makefile           |    1 +
>  drivers/gpu/drm/i915/i915_debugfs.c     |    2 +-
>  drivers/gpu/drm/i915/i915_drv.h         |   37 +-
>  drivers/gpu/drm/i915/intel_audio.c      |    2 +-
>  drivers/gpu/drm/i915/intel_cdclk.c      | 1867
> +++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/intel_display.c    | 1831 ++----------------------------
>  drivers/gpu/drm/i915/intel_dp.c         |    4 +-
>  drivers/gpu/drm/i915/intel_drv.h        |   43 +-
>  drivers/gpu/drm/i915/intel_fbc.c        |    5 +-
>  drivers/gpu/drm/i915/intel_panel.c      |    4 +-
>  drivers/gpu/drm/i915/intel_pm.c         |   51 +-
>  drivers/gpu/drm/i915/intel_runtime_pm.c |    6 +-
>  13 files changed, 2042 insertions(+), 1820 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_cdclk.c
>