[Intel-gfx] [PATCH 2/6] drm/i915: Remove BXT incoherent seqno write workaround

[Ville Syrjälä]

On Mon, Jan 23, 2017 at 01:05:57PM +0000, Chris Wilson wrote:
> This w/a was only used for preproduction hw, which is no longer in use.
> Remove the workaround to simplify the code.
> 
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala at linux.intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen at linux.intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin at intel.com>
> ---
>  drivers/gpu/drm/i915/intel_lrc.c | 17 -----------------
>  1 file changed, 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
> index 8ffa4961aa40..202ce1e6e499 100644
> --- a/drivers/gpu/drm/i915/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/intel_lrc.c
> @@ -1638,21 +1638,6 @@ static int gen8_emit_flush_render(struct drm_i915_gem_request *request,
>  	return 0;
>  }
>  
> -static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
> -{
> -	/*
> -	 * On BXT A steppings there is a HW coherency issue whereby the
> -	 * MI_STORE_DATA_IMM storing the completed request's seqno
> -	 * occasionally doesn't invalidate the CPU cache. Work around this by
> -	 * clflushing the corresponding cacheline whenever the caller wants
> -	 * the coherency to be guaranteed. Note that this cacheline is known
> -	 * to be clean at this point, since we only write it in
> -	 * bxt_a_set_seqno(), where we also do a clflush after the write. So
> -	 * this clflush in practice becomes an invalidate operation.
> -	 */
> -	intel_flush_status_page(engine, I915_GEM_HWS_INDEX);
> -}

Ahem. Don't we have hardware in the pipeline which is going to need
this stuff?

> -
>  /*
>   * Reserve space for 2 NOOPs at the end of each request to be
>   * used as a workaround for not being allowed to do lite
> @@ -1800,8 +1785,6 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>  	engine->irq_enable = gen8_logical_ring_enable_irq;
>  	engine->irq_disable = gen8_logical_ring_disable_irq;
>  	engine->emit_bb_start = gen8_emit_bb_start;
> -	if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1))
> -		engine->irq_seqno_barrier = bxt_a_seqno_barrier;
>  }
>  
>  static inline void
> -- 
> 2.11.0
> 
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-- 
Ville Syrjälä
Intel OTC