[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Unify the HSW/BDW and GEN9+ power well code

[Patchwork]

== Series Details ==

Series: drm/i915: Unify the HSW/BDW and GEN9+ power well code
URL   : https://patchwork.freedesktop.org/series/26922/
State : success

== Summary ==

Series 26922v1 drm/i915: Unify the HSW/BDW and GEN9+ power well code
https://patchwork.freedesktop.org/api/1.0/series/26922/revisions/1/mbox/

Test gem_exec_suspend:
        Subgroup basic-s4-devices:
                dmesg-warn -> PASS       (fi-kbl-7560u) fdo#100125
Test kms_pipe_crc_basic:
        Subgroup hang-read-crc-pipe-a:
                dmesg-warn -> PASS       (fi-pnv-d510) fdo#101597

fdo#100125 https://bugs.freedesktop.org/show_bug.cgi?id=100125
fdo#101597 https://bugs.freedesktop.org/show_bug.cgi?id=101597

fi-bdw-5557u     total:279  pass:268  dwarn:0   dfail:0   fail:0   skip:11  time:444s
fi-bdw-gvtdvm    total:279  pass:265  dwarn:0   dfail:0   fail:0   skip:14  time:435s
fi-blb-e6850     total:279  pass:224  dwarn:1   dfail:0   fail:0   skip:54  time:360s
fi-bsw-n3050     total:279  pass:243  dwarn:0   dfail:0   fail:0   skip:36  time:523s
fi-bxt-j4205     total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:504s
fi-byt-j1900     total:279  pass:254  dwarn:1   dfail:0   fail:0   skip:24  time:489s
fi-byt-n2820     total:279  pass:250  dwarn:1   dfail:0   fail:0   skip:28  time:485s
fi-glk-2a        total:279  pass:260  dwarn:0   dfail:0   fail:0   skip:19  time:598s
fi-hsw-4770      total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:434s
fi-hsw-4770r     total:279  pass:263  dwarn:0   dfail:0   fail:0   skip:16  time:410s
fi-ilk-650       total:279  pass:229  dwarn:0   dfail:0   fail:0   skip:50  time:420s
fi-ivb-3520m     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:484s
fi-kbl-7500u     total:279  pass:261  dwarn:0   dfail:0   fail:0   skip:18  time:459s
fi-kbl-7560u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:577s
fi-kbl-r         total:279  pass:260  dwarn:1   dfail:0   fail:0   skip:18  time:583s
fi-pnv-d510      total:279  pass:223  dwarn:1   dfail:0   fail:0   skip:55  time:560s
fi-skl-6260u     total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:460s
fi-skl-6700hq    total:279  pass:262  dwarn:0   dfail:0   fail:0   skip:17  time:586s
fi-skl-6700k     total:279  pass:257  dwarn:4   dfail:0   fail:0   skip:18  time:466s
fi-skl-6770hq    total:279  pass:269  dwarn:0   dfail:0   fail:0   skip:10  time:486s
fi-skl-gvtdvm    total:279  pass:266  dwarn:0   dfail:0   fail:0   skip:13  time:437s
fi-snb-2520m     total:279  pass:251  dwarn:0   dfail:0   fail:0   skip:28  time:544s
fi-snb-2600      total:279  pass:250  dwarn:0   dfail:0   fail:0   skip:29  time:406s

13173bea86ebf8643a32b8373eeadd3fdcd1cc4d drm-tip: 2017y-07m-06d-14h-15m-52s UTC integration manifest
7901382 drm/i915: Gather all the power well->domain mappings to one place
0975571 drm/i915: Move hsw_power_well_enable() next to the rest of HSW helpers
fe0d218 drm/i915/gen9+: Unify the HSW/BDW and GEN9+ power well helpers
7c8c876 drm/i915/hsw+: Add has_fuses power well attribute
367da6b drm/i915/hsw, bdw: Wait for the power well disabled state
f530fd8 drm/i915/hsw, bdw: Add irq_pipe_mask, has_vga power well attributes
62c6606 drm/i915/hsw+: Unify the hsw/bdw and gen9+ power well req/state macros
7356e02 drm/i915/hsw, bdw: Split power well set to enable/disable helpers
52a5d3d drm/i915/hsw, bdw: Remove redundant state check during power well toggling
401d3f1 drm/i915/gen9+: Remove redundant state check during power well toggling
7b08a87 drm/i915/gen9+: Remove redundant power well state assert during enabling
16f9234 drm/i915/bxt, glk: Give a proper name to the power well struct phy field
1a2425c drm/i915: Check for duplicated power well IDs
1057bcf drm/i915/hsw, bdw: Add an ID for the global display power well
6660ee8 drm/i915/gen2: Add an ID for the display pipes power well
853a3d6 drm/i915: Assign everywhere the always-on power well ID
10c6a6b drm/i915: Unify power well ID enums
4e96740 drm/i915/chv: Add unique power well ID for the pipe A power well

== Logs ==

For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_5126/