[Intel-gfx] [PATCH] drm/i915/cnl: Inherit RPS stuff from previous platforms.
David Weinehall
david.weinehall at linux.intel.com
Fri Jul 7 12:03:24 UTC 2017
On Thu, Jul 06, 2017 at 01:41:13PM -0700, Rodrigo Vivi wrote:
> Apparently no change on RPS stuff from previous platforms.
>
> v2: Merging to rps related patches in one and also adding
> missed cases.
>
> Cc: David Weinehall <david.weinehall at intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
Double-checking BSpec didn't yield anything obvious, so:
Reviewed-by: David Weinehall <david.weinehall at linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 20 ++++++++++++--------
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> drivers/gpu/drm/i915/i915_sysfs.c | 2 +-
> drivers/gpu/drm/i915/intel_pm.c | 18 +++++++++---------
> 4 files changed, 24 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 643f56b..ca2e34b 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1159,7 +1159,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
>
> reqf = I915_READ(GEN6_RPNSWREQ);
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> reqf >>= 23;
> else {
> reqf &= ~GEN6_TURBO_DISABLE;
> @@ -1181,7 +1181,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
> rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
> rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> @@ -1210,7 +1210,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> dev_priv->rps.pm_intrmsk_mbz);
> seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
> seq_printf(m, "Render p-state ratio: %d\n",
> - (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
> + (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
> seq_printf(m, "Render p-state VID: %d\n",
> gt_perf_status & 0xff);
> seq_printf(m, "Render p-state limit: %d\n",
> @@ -1241,18 +1241,21 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
>
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
> rp_state_cap >> 16) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + max_freq *= (IS_GEN9_BC(dev_priv) ||
> + IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (rp_state_cap & 0xff00) >> 8;
> - max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + max_freq *= (IS_GEN9_BC(dev_priv) ||
> + IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
>
> max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
> rp_state_cap >> 0) & 0xff;
> - max_freq *= (IS_GEN9_BC(dev_priv) ? GEN9_FREQ_SCALER : 1);
> + max_freq *= (IS_GEN9_BC(dev_priv) ||
> + IS_CANNONLAKE(dev_priv) ? GEN9_FREQ_SCALER : 1);
> seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
> intel_gpu_freq(dev_priv, max_freq));
> seq_printf(m, "Max overclocked frequency: %dMHz\n",
> @@ -1855,7 +1858,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> if (ret)
> goto out;
>
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq =
> dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
> @@ -1875,7 +1878,8 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
> &ia_freq);
> seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
> intel_gpu_freq(dev_priv, (gpu_freq *
> - (IS_GEN9_BC(dev_priv) ?
> + (IS_GEN9_BC(dev_priv) ||
> + IS_CANNONLAKE(dev_priv) ?
> GEN9_FREQ_SCALER : 1))),
> ((ia_freq >> 0) & 0xff) * 100,
> ((ia_freq >> 8) & 0xff) * 100);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 64cc674..21ab12f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3522,7 +3522,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_28_US(us) roundup(((us) * 100) >> 7, 25)
> #define INTERVAL_1_33_US(us) (((us) * 3) >> 2)
> #define INTERVAL_0_833_US(us) (((us) * 6) / 5)
> -#define GT_INTERVAL_FROM_US(dev_priv, us) (IS_GEN9(dev_priv) ? \
> +#define GT_INTERVAL_FROM_US(dev_priv, us) (INTEL_GEN(dev_priv) >= 9 ? \
> (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_US(us) : \
> INTERVAL_1_33_US(us)) : \
> @@ -3531,7 +3531,7 @@ enum skl_disp_power_wells {
> #define INTERVAL_1_28_TO_US(interval) (((interval) << 7) / 100)
> #define INTERVAL_1_33_TO_US(interval) (((interval) << 2) / 3)
> #define INTERVAL_0_833_TO_US(interval) (((interval) * 5) / 6)
> -#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (IS_GEN9(dev_priv) ? \
> +#define GT_PM_INTERVAL_TO_US(dev_priv, interval) (INTEL_GEN(dev_priv) >= 9 ? \
> (IS_GEN9_LP(dev_priv) ? \
> INTERVAL_0_833_TO_US(interval) : \
> INTERVAL_1_33_TO_US(interval)) : \
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 3736c9f..7fcf006 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -253,7 +253,7 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
> ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> } else {
> u32 rpstat = I915_READ(GEN6_RPSTAT1);
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> ret = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> ret = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c3fcadf..6db833e 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -5852,7 +5852,7 @@ static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
> * the hw runs at the minimal clock before selecting the desired
> * frequency, if the down threshold expires in that window we will not
> * receive a down interrupt. */
> - if (IS_GEN9(dev_priv)) {
> + if (INTEL_GEN(dev_priv) >= 9) {
> limits = (dev_priv->rps.max_freq_softlimit) << 23;
> if (val <= dev_priv->rps.min_freq_softlimit)
> limits |= (dev_priv->rps.min_freq_softlimit) << 14;
> @@ -5994,7 +5994,7 @@ static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
> if (val != dev_priv->rps.cur_freq) {
> gen6_set_rps_thresholds(dev_priv, val);
>
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> I915_WRITE(GEN6_RPNSWREQ,
> GEN9_FREQUENCY(val));
> else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> @@ -6353,7 +6353,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
>
> dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
> - IS_GEN9_BC(dev_priv)) {
> + IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> u32 ddcc_status = 0;
>
> if (sandybridge_pcode_read(dev_priv,
> @@ -6366,7 +6366,7 @@ static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
> dev_priv->rps.max_freq);
> }
>
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> /* Store the frequency values in 16.66 MHZ units, which is
> * the natural hardware unit for SKL
> */
> @@ -6672,7 +6672,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> /* convert DDR frequency from units of 266.6MHz to bandwidth */
> min_ring_freq = mult_frac(min_ring_freq, 8, 3);
>
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> /* Convert GT frequency to 50 HZ units */
> min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
> max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
> @@ -6690,7 +6690,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
> int diff = max_gpu_freq - gpu_freq;
> unsigned int ia_freq = 0, ring_freq = 0;
>
> - if (IS_GEN9_BC(dev_priv)) {
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) {
> /*
> * ring_freq = 2 * GT. ring_freq is in 100MHz units
> * No floor required for ring frequency on SKL.
> @@ -7821,7 +7821,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
> } else if (INTEL_GEN(dev_priv) >= 9) {
> gen9_enable_rc6(dev_priv);
> gen9_enable_rps(dev_priv);
> - if (IS_GEN9_BC(dev_priv))
> + if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv))
> gen6_update_ring_freq(dev_priv);
> } else if (IS_BROADWELL(dev_priv)) {
> gen8_enable_rps(dev_priv);
> @@ -9066,7 +9066,7 @@ static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
>
> int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
> {
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
> GEN9_FREQ_SCALER);
> else if (IS_CHERRYVIEW(dev_priv))
> @@ -9079,7 +9079,7 @@ int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
>
> int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
> {
> - if (IS_GEN9(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 9)
> return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
> GT_FREQUENCY_MULTIPLIER);
> else if (IS_CHERRYVIEW(dev_priv))
> --
> 1.9.1
>
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