[Intel-gfx] [PATCH 1/3] drm/i915/lrc: allocate separate page for HWSP

[Chris Wilson]

Quoting Michel Thierry (2017-07-13 00:51:11)
> On 7/12/2017 3:57 PM, Chris Wilson wrote:
> > From: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> > 
> > On gen8+ we're currently using the PPHWSP of the kernel ctx as the
> > global HWSP. However, when the kernel ctx gets submitted (e.g. from
> > __intel_autoenable_gt_powersave) the HW will use that page as both
> > HWSP and PPHWSP. This causes a conflict in the register arena of the
> > HWSP, i.e. offsets below 0x80. We don't current utilize this arena,
> > but in the following patches we will take advantage of the cached
> > register state for handling execlist's context status interrupt.
> > 
> > To avoid the conflict, instead of re-using the PPHWSP of the kernel
> > ctx we can allocate a separate page for the HWSP like what happens for
> > pre-execlists platform.
> > 
> 
> I'm sure you haven't forgotten, but anyway a reminder for others; this 
> change depends on "drm/i915/guc: Don't make assumptions while getting 
> the lrca offset" [https://patchwork.freedesktop.org/patch/166519/], or 
> guc loading will break.
> 
> > v2: Add a use-case for the register arena.
> > 
> 
> s/arena/area/ ?

I like arena when I want the impression of an enclosed space, and area
for an open space. Here I felt that the registers are a reserved block
inside the hwsp, which I felt acted like an enclosure.
-Chris