[Intel-gfx] [PATCH v2 1/3] drm/i915/gvt: Add framebuffer decoder support

Zhenyu Wang zhenyuw at linux.intel.com
Mon Jul 17 04:14:34 UTC 2017


On 2017.07.17 11:06:24 +0800, Tina Zhang wrote:
> Framebuffer decoder returns guest framebuffer information.
> Guest framebuffer includes primary, cursor and sprite plane.
> 
> Signed-off-by: Xiaoguang Chen <xiaoguang.chen at intel.com>
> Signed-off-by: Tina Zhang <tina.zhang at intel.com>
> ---
>  drivers/gpu/drm/i915/gvt/Makefile     |   3 +-
>  drivers/gpu/drm/i915/gvt/display.c    |   2 +-
>  drivers/gpu/drm/i915/gvt/display.h    |   2 +
>  drivers/gpu/drm/i915/gvt/fb_decoder.c | 429 ++++++++++++++++++++++++++++++++++
>  drivers/gpu/drm/i915/gvt/fb_decoder.h | 175 ++++++++++++++
>  drivers/gpu/drm/i915/gvt/gvt.h        |   1 +
>  6 files changed, 610 insertions(+), 2 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
>  create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h
> 
> diff --git a/drivers/gpu/drm/i915/gvt/Makefile b/drivers/gpu/drm/i915/gvt/Makefile
> index f5486cb9..019d596 100644
> --- a/drivers/gpu/drm/i915/gvt/Makefile
> +++ b/drivers/gpu/drm/i915/gvt/Makefile
> @@ -1,7 +1,8 @@
>  GVT_DIR := gvt
>  GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
>  	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
> -	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
> +	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
> +	fb_decoder.o
>  
>  ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR)
>  i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
> diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
> index 2deb05f..58d90cf 100644
> --- a/drivers/gpu/drm/i915/gvt/display.c
> +++ b/drivers/gpu/drm/i915/gvt/display.c
> @@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
>  	return 1;
>  }
>  
> -static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
> +int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
>  {
>  	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
>  
> diff --git a/drivers/gpu/drm/i915/gvt/display.h b/drivers/gpu/drm/i915/gvt/display.h
> index d73de22..b46b868 100644
> --- a/drivers/gpu/drm/i915/gvt/display.h
> +++ b/drivers/gpu/drm/i915/gvt/display.h
> @@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
>  void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
>  void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
>  
> +int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
> +
>  #endif
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> new file mode 100644
> index 0000000..2bd5b3c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c
> @@ -0,0 +1,429 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + * Authors:
> + *    Kevin Tian <kevin.tian at intel.com>
> + *
> + * Contributors:
> + *    Bing Niu <bing.niu at intel.com>
> + *    Xu Han <xu.han at intel.com>
> + *    Ping Gao <ping.a.gao at intel.com>
> + *    Xiaoguang Chen <xiaoguang.chen at intel.com>
> + *    Yang Liu <yang2.liu at intel.com>
> + *    Tina Zhang <tina.zhang at intel.com>
> + *
> + */
> +
> +#include <uapi/drm/drm_fourcc.h>
> +#include "i915_drv.h"
> +#include "gvt.h"
> +
> +#define PRIMARY_FORMAT_NUM	16
> +struct pixel_format {
> +	int	drm_format;	/* Pixel format in DRM definition */
> +	int	bpp;		/* Bits per pixel, 0 indicates invalid */
> +	char *desc;		/* The description */
> +};
> +
> +/* non-supported format has bpp default to 0 */
> +static struct pixel_format bdw_pixel_formats[PRIMARY_FORMAT_NUM] = {
> +	[0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
> +	[0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
> +	[0x6] = {DRM_FORMAT_XRGB8888, 32,
> +		"32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
> +	[0x8] = {DRM_FORMAT_XBGR2101010, 32,
> +		"32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
> +	[0xa] = {DRM_FORMAT_XRGB2101010, 32,
> +		"32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
> +	[0xe] = {DRM_FORMAT_XBGR8888, 32,
> +		"32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
> +};

Might be better to use same index lookup method as skl formats,
instead of used for array index directly.

> +
> +/* non-supported format has bpp default to 0 */
> +static struct pixel_format skl_pixel_formats[] = {
> +	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
> +	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
> +	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
> +	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
> +
> +	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
> +	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
> +	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
> +	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
> +
> +	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
> +	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
> +	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
> +	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
> +
> +
> +	/* non-supported format has bpp default to 0 */
> +	{0, 0, NULL},
> +};
> +
> +static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
> +	int yuv_order)
> +{
> +	int skl_pixel_formats_index = 14;
> +
> +	switch (format) {
> +	case PLANE_CTL_FORMAT_INDEXED:
> +		skl_pixel_formats_index = 4;
> +		break;
> +	case PLANE_CTL_FORMAT_RGB_565:
> +		skl_pixel_formats_index = 5;
> +		break;
> +	case PLANE_CTL_FORMAT_XRGB_8888:
> +		if (rgb_order)
> +			skl_pixel_formats_index = alpha ? 6 : 7;
> +		else
> +			skl_pixel_formats_index = alpha ? 8 : 9;
> +		break;
> +	case PLANE_CTL_FORMAT_XRGB_2101010:
> +		skl_pixel_formats_index = rgb_order ? 10 : 11;
> +		break;
> +	case PLANE_CTL_FORMAT_YUV422:
> +		skl_pixel_formats_index = yuv_order >> 16;
> +		if (skl_pixel_formats_index > 3)
> +			return -EINVAL;
> +		break;
> +
> +	default:
> +		break;
> +	}
> +
> +	return skl_pixel_formats_index;
> +}
> +
> +static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
> +	u32 tiled, int stride_mask, int bpp)
> +{
> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> +
> +	u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
> +	u32 stride = stride_reg;
> +
> +	if (IS_SKYLAKE(dev_priv)) {
> +		switch (tiled) {
> +		case PLANE_CTL_TILED_LINEAR:
> +			stride = stride_reg * 64;
> +			break;
> +		case PLANE_CTL_TILED_X:
> +			stride = stride_reg * 512;
> +			break;
> +		case PLANE_CTL_TILED_Y:
> +			stride = stride_reg * 128;
> +			break;
> +		case PLANE_CTL_TILED_YF:
> +			if (bpp == 8)
> +				stride = stride_reg * 64;
> +			else if (bpp == 16 || bpp == 32 || bpp == 64)
> +				stride = stride_reg * 128;
> +			else
> +				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
> +			break;
> +		default:
> +			gvt_dbg_core("skl: unsupported tile format:%x\n",
> +				tiled);
> +		}
> +	}
> +
> +	return stride;
> +}
> +
> +static int get_active_pipe(struct intel_vgpu *vgpu)
> +{
> +	int i;
> +
> +	for (i = 0; i < I915_MAX_PIPES; i++)
> +		if (pipe_is_enabled(vgpu, i))
> +			break;
> +
> +	return i;
> +}
> +
> +/**
> + * intel_vgpu_decode_primary_plane - Decode primary plane
> + * @vgpu: input vgpu
> + * @plane: primary plane to save decoded info
> + * This function is called for decoding plane
> + *
> + * Returns:
> + * 0 on success, non-zero if failed.
> + */
> +int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_primary_plane_format *plane)
> +{
> +	u32 val, fmt;
> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> +	int pipe;
> +
> +	pipe = get_active_pipe(vgpu);
> +	if (pipe >= I915_MAX_PIPES)
> +		return -ENODEV;
> +
> +	val = vgpu_vreg(vgpu, DSPCNTR(pipe));
> +	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
> +	if (!plane->enabled)
> +		return -ENODEV;
> +
> +	if (IS_SKYLAKE(dev_priv)) {
> +		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
> +		_PLANE_CTL_TILED_SHIFT;
> +		fmt = skl_format_to_drm(
> +			val & PLANE_CTL_FORMAT_MASK,
> +			val & PLANE_CTL_ORDER_RGBX,
> +			val & PLANE_CTL_ALPHA_MASK,
> +			val & PLANE_CTL_YUV422_ORDER_MASK);
> +		plane->bpp = skl_pixel_formats[fmt].bpp;
> +		plane->drm_format = skl_pixel_formats[fmt].drm_format;
> +	} else {
> +		plane->tiled = !!(val & DISPPLANE_TILED);
> +		fmt = (val & DISPPLANE_PIXFORMAT_MASK) >> _PRI_PLANE_FMT_SHIFT;
> +		plane->bpp = bdw_pixel_formats[fmt].bpp;
> +		plane->drm_format = bdw_pixel_formats[fmt].drm_format;
> +	}
> +
> +	if (!plane->bpp) {
> +		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
> +		return -EINVAL;
> +	}
> +
> +	plane->hw_format = fmt;
> +
> +	plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & GTT_PAGE_MASK;
> +	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
> +	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
> +		gvt_vgpu_err("invalid gma address: %lx\n",
> +				(unsigned long)plane->base);

Not return error? And even better to check base with
intel_gvt_ggtt_validate_range(vgpu, base, 0) first.

> +	}
> +
> +	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
> +		(IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) :
> +		_PRI_PLANE_STRIDE_MASK, plane->bpp);
> +
> +	plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
> +		_PIPE_H_SRCSZ_SHIFT;
> +	plane->width += 1;
> +	plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) &
> +			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
> +	plane->height += 1;	/* raw height is one minus the real value */
> +
> +	val = vgpu_vreg(vgpu, DSPTILEOFF(pipe));
> +	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
> +		_PRI_PLANE_X_OFF_SHIFT;
> +	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
> +		_PRI_PLANE_Y_OFF_SHIFT;
> +
> +	return 0;
> +}
> +
> +#define CURSOR_FORMAT_NUM	(1 << 6)
> +struct cursor_mode_format {
> +	int	drm_format;	/* Pixel format in DRM definition */
> +	u8	bpp;		/* Bits per pixel; 0 indicates invalid */
> +	u32	width;		/* In pixel */
> +	u32	height;		/* In lines */
> +	char	*desc;		/* The description */
> +};
> +
> +/* non-supported format has bpp default to 0 */
> +static struct cursor_mode_format cursor_pixel_formats[CURSOR_FORMAT_NUM] = {
> +	[0x22]  = {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
> +	[0x23]  = {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
> +	[0x27]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
> +	[0x7]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
> +};

For only four formats to use all that space, could just look them up?

> +
> +/**
> + * intel_vgpu_decode_cursor_plane - Decode sprite plane
> + * @vgpu: input vgpu
> + * @plane: cursor plane to save decoded info
> + * This function is called for decoding plane
> + *
> + * Returns:
> + * 0 on success, non-zero if failed.
> + */
> +int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_cursor_plane_format *plane)
> +{
> +	u32 val, mode;
> +	u32 alpha_plane, alpha_force;
> +	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
> +	int pipe;
> +
> +	pipe = get_active_pipe(vgpu);
> +	if (pipe >= I915_MAX_PIPES)
> +		return -ENODEV;
> +
> +	val = vgpu_vreg(vgpu, CURCNTR(pipe));
> +	mode = val & CURSOR_MODE;
> +	plane->enabled = (mode != CURSOR_MODE_DISABLE);
> +	if (!plane->enabled)
> +		return -ENODEV;
> +
> +	if (!cursor_pixel_formats[mode].bpp) {
> +		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
> +		return -EINVAL;
> +	}
> +	plane->mode = mode;
> +	plane->bpp = cursor_pixel_formats[mode].bpp;
> +	plane->drm_format = cursor_pixel_formats[mode].drm_format;
> +	plane->width = cursor_pixel_formats[mode].width;
> +	plane->height = cursor_pixel_formats[mode].height;
> +
> +	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
> +				_CURSOR_ALPHA_PLANE_SHIFT;
> +	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
> +				_CURSOR_ALPHA_FORCE_SHIFT;
> +	if (alpha_plane || alpha_force)
> +		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
> +			alpha_plane, alpha_force);
> +
> +	plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & GTT_PAGE_MASK;
> +	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
> +	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
> +		gvt_vgpu_err("invalid gma address: %lx\n",
> +				(unsigned long)plane->base);

ditto

> +	}
> +
> +	val = vgpu_vreg(vgpu, CURPOS(pipe));
> +	plane->x_pos = (val & _CURSOR_POS_X_MASK) >> _CURSOR_POS_X_SHIFT;
> +	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >> _CURSOR_SIGN_X_SHIFT;
> +	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >> _CURSOR_POS_Y_SHIFT;
> +	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >> _CURSOR_SIGN_Y_SHIFT;
> +
> +	return 0;
> +}
> +
> +#define SPRITE_FORMAT_NUM	(1 << 3)
> +
> +static struct pixel_format sprite_pixel_formats[SPRITE_FORMAT_NUM] = {
> +	[0x0]  = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
> +	[0x1]  = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
> +	[0x2]  = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
> +	[0x4] = {DRM_FORMAT_AYUV, 32,
> +		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
> +};
> +
> +/**
> + * intel_vgpu_decode_sprite_plane - Decode sprite plane
> + * @vgpu: input vgpu
> + * @plane: sprite plane to save decoded info
> + * This function is called for decoding plane
> + *
> + * Returns:
> + * 0 on success, non-zero if failed.
> + */
> +int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_sprite_plane_format *plane)
> +{
> +	u32 val, fmt;
> +	u32 color_order, yuv_order;
> +	int drm_format;
> +	int pipe;
> +
> +	pipe = get_active_pipe(vgpu);
> +	if (pipe >= I915_MAX_PIPES)
> +		return -ENODEV;
> +
> +	val = vgpu_vreg(vgpu, SPRCTL(pipe));
> +	plane->enabled = !!(val & SPRITE_ENABLE);
> +	if (!plane->enabled)
> +		return -ENODEV;
> +
> +	plane->tiled = !!(val & SPRITE_TILED);
> +	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
> +	yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
> +				_SPRITE_YUV_ORDER_SHIFT;
> +
> +	fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
> +	if (!sprite_pixel_formats[fmt].bpp) {
> +		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
> +		return -EINVAL;
> +	}
> +	plane->hw_format = fmt;
> +	plane->bpp = sprite_pixel_formats[fmt].bpp;
> +	drm_format = sprite_pixel_formats[fmt].drm_format;
> +
> +	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
> +	 * BGR depending on the state of the color_order field
> +	 */
> +	if (!color_order) {
> +		if (drm_format == DRM_FORMAT_XRGB2101010)
> +			drm_format = DRM_FORMAT_XBGR2101010;
> +		else if (drm_format == DRM_FORMAT_XRGB8888)
> +			drm_format = DRM_FORMAT_XBGR8888;
> +	}
> +
> +	if (drm_format == DRM_FORMAT_YUV422) {
> +		switch (yuv_order) {
> +		case 0:
> +			drm_format = DRM_FORMAT_YUYV;
> +			break;
> +		case 1:
> +			drm_format = DRM_FORMAT_UYVY;
> +			break;
> +		case 2:
> +			drm_format = DRM_FORMAT_YVYU;
> +			break;
> +		case 3:
> +			drm_format = DRM_FORMAT_VYUY;
> +			break;
> +		default:
> +			/* yuv_order has only 2 bits */
> +			break;
> +		}
> +	}
> +
> +	plane->drm_format = drm_format;
> +
> +	plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & GTT_PAGE_MASK;
> +	plane->base_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm, plane->base);
> +	if (plane->base_gpa == INTEL_GVT_INVALID_ADDR) {
> +		gvt_vgpu_err("invalid gma address: %lx\n",
> +				(unsigned long)plane->base);

ditto

> +	}
> +
> +	plane->stride = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) &
> +				_SPRITE_STRIDE_MASK;
> +
> +	val = vgpu_vreg(vgpu, SPRSIZE(pipe));
> +	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
> +		_SPRITE_SIZE_HEIGHT_SHIFT;
> +	plane->width = (val & _SPRITE_SIZE_WIDTH_MASK) >>
> +		_SPRITE_SIZE_WIDTH_SHIFT;
> +	plane->height += 1;	/* raw height is one minus the real value */
> +	plane->width += 1;	/* raw width is one minus the real value */
> +
> +	val = vgpu_vreg(vgpu, SPRPOS(pipe));
> +	plane->x_pos = (val & _SPRITE_POS_X_MASK) >> _SPRITE_POS_X_SHIFT;
> +	plane->y_pos = (val & _SPRITE_POS_Y_MASK) >> _SPRITE_POS_Y_SHIFT;
> +
> +	val = vgpu_vreg(vgpu, SPROFFSET(pipe));
> +	plane->x_offset = (val & _SPRITE_OFFSET_START_X_MASK) >>
> +			   _SPRITE_OFFSET_START_X_SHIFT;
> +	plane->y_offset = (val & _SPRITE_OFFSET_START_Y_MASK) >>
> +			   _SPRITE_OFFSET_START_Y_SHIFT;
> +
> +	return 0;
> +}
> diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.h b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> new file mode 100644
> index 0000000..51a7e97
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.h
> @@ -0,0 +1,175 @@
> +/*
> + * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
> + * SOFTWARE.
> + *
> + * Authors:
> + *    Kevin Tian <kevin.tian at intel.com>
> + *
> + * Contributors:
> + *    Bing Niu <bing.niu at intel.com>
> + *    Xu Han <xu.han at intel.com>
> + *    Ping Gao <ping.a.gao at intel.com>
> + *    Xiaoguang Chen <xiaoguang.chen at intel.com>
> + *    Yang Liu <yang2.liu at intel.com>
> + *    Tina Zhang <tina.zhang at intel.com>
> + *
> + */
> +
> +#ifndef _GVT_FB_DECODER_H_
> +#define _GVT_FB_DECODER_H_
> +
> +#define _PLANE_CTL_FORMAT_SHIFT		24
> +#define _PLANE_CTL_TILED_SHIFT		10
> +#define _PIPE_V_SRCSZ_SHIFT		0
> +#define _PIPE_V_SRCSZ_MASK		(0xfff << _PIPE_V_SRCSZ_SHIFT)
> +#define _PIPE_H_SRCSZ_SHIFT		16
> +#define _PIPE_H_SRCSZ_MASK		(0x1fff << _PIPE_H_SRCSZ_SHIFT)
> +
> +#define _PRI_PLANE_FMT_SHIFT		26
> +#define _PRI_PLANE_STRIDE_MASK		(0x3ff << 6)
> +#define _PRI_PLANE_X_OFF_SHIFT		0
> +#define _PRI_PLANE_X_OFF_MASK		(0x1fff << _PRI_PLANE_X_OFF_SHIFT)
> +#define _PRI_PLANE_Y_OFF_SHIFT		16
> +#define _PRI_PLANE_Y_OFF_MASK		(0xfff << _PRI_PLANE_Y_OFF_SHIFT)
> +
> +#define _CURSOR_MODE			0x3f
> +#define _CURSOR_ALPHA_FORCE_SHIFT	8
> +#define _CURSOR_ALPHA_FORCE_MASK	(0x3 << _CURSOR_ALPHA_FORCE_SHIFT)
> +#define _CURSOR_ALPHA_PLANE_SHIFT	10
> +#define _CURSOR_ALPHA_PLANE_MASK	(0x3 << _CURSOR_ALPHA_PLANE_SHIFT)
> +#define _CURSOR_POS_X_SHIFT		0
> +#define _CURSOR_POS_X_MASK		(0x1fff << _CURSOR_POS_X_SHIFT)
> +#define _CURSOR_SIGN_X_SHIFT		15
> +#define _CURSOR_SIGN_X_MASK		(1 << _CURSOR_SIGN_X_SHIFT)
> +#define _CURSOR_POS_Y_SHIFT		16
> +#define _CURSOR_POS_Y_MASK		(0xfff << _CURSOR_POS_Y_SHIFT)
> +#define _CURSOR_SIGN_Y_SHIFT		31
> +#define _CURSOR_SIGN_Y_MASK		(1 << _CURSOR_SIGN_Y_SHIFT)
> +
> +#define _SPRITE_FMT_SHIFT		25
> +#define _SPRITE_COLOR_ORDER_SHIFT	20
> +#define _SPRITE_YUV_ORDER_SHIFT		16
> +#define _SPRITE_STRIDE_SHIFT		6
> +#define _SPRITE_STRIDE_MASK		(0x1ff << _SPRITE_STRIDE_SHIFT)
> +#define _SPRITE_SIZE_WIDTH_SHIFT	0
> +#define _SPRITE_SIZE_HEIGHT_SHIFT	16
> +#define _SPRITE_SIZE_WIDTH_MASK		(0x1fff << _SPRITE_SIZE_WIDTH_SHIFT)
> +#define _SPRITE_SIZE_HEIGHT_MASK	(0xfff << _SPRITE_SIZE_HEIGHT_SHIFT)
> +#define _SPRITE_POS_X_SHIFT		0
> +#define _SPRITE_POS_Y_SHIFT		16
> +#define _SPRITE_POS_X_MASK		(0x1fff << _SPRITE_POS_X_SHIFT)
> +#define _SPRITE_POS_Y_MASK		(0xfff << _SPRITE_POS_Y_SHIFT)
> +#define _SPRITE_OFFSET_START_X_SHIFT	0
> +#define _SPRITE_OFFSET_START_Y_SHIFT	16
> +#define _SPRITE_OFFSET_START_X_MASK	(0x1fff << _SPRITE_OFFSET_START_X_SHIFT)
> +#define _SPRITE_OFFSET_START_Y_MASK	(0xfff << _SPRITE_OFFSET_START_Y_SHIFT)
> +
> +enum GVT_FB_EVENT {
> +	FB_MODE_SET_START = 1,
> +	FB_MODE_SET_END,
> +	FB_DISPLAY_FLIP,
> +};
> +
> +enum DDI_PORT {
> +	DDI_PORT_NONE	= 0,
> +	DDI_PORT_B	= 1,
> +	DDI_PORT_C	= 2,
> +	DDI_PORT_D	= 3,
> +	DDI_PORT_E	= 4
> +};
> +
> +struct intel_gvt;
> +
> +struct gvt_fb_notify_msg {
> +	unsigned int vm_id;
> +	unsigned int pipe_id; /* id starting from 0 */
> +	unsigned int plane_id; /* primary, cursor, or sprite */
> +};

no usage

> +
> +/* color space conversion and gamma correction are not included */
> +struct intel_vgpu_primary_plane_format {
> +	u8	enabled;	/* plane is enabled */
> +	u8	tiled;		/* X-tiled */
> +	u8	bpp;		/* bits per pixel */
> +	u32	hw_format;	/* format field in the PRI_CTL register */
> +	u32	drm_format;	/* format in DRM definition */
> +	u32	base;		/* framebuffer base in graphics memory */
> +	u64     base_gpa;
> +	u32	x_offset;	/* in pixels */
> +	u32	y_offset;	/* in lines */
> +	u32	width;		/* in pixels */
> +	u32	height;		/* in lines */
> +	u32	stride;		/* in bytes */
> +};
> +
> +struct intel_vgpu_sprite_plane_format {
> +	u8	enabled;	/* plane is enabled */
> +	u8	tiled;		/* X-tiled */
> +	u8	bpp;		/* bits per pixel */
> +	u32	hw_format;	/* format field in the SPR_CTL register */
> +	u32	drm_format;	/* format in DRM definition */
> +	u32	base;		/* sprite base in graphics memory */
> +	u64     base_gpa;
> +	u32	x_pos;		/* in pixels */
> +	u32	y_pos;		/* in lines */
> +	u32	x_offset;	/* in pixels */
> +	u32	y_offset;	/* in lines */
> +	u32	width;		/* in pixels */
> +	u32	height;		/* in lines */
> +	u32	stride;		/* in bytes */
> +};
> +
> +struct intel_vgpu_cursor_plane_format {
> +	u8	enabled;
> +	u8	mode;		/* cursor mode select */
> +	u8	bpp;		/* bits per pixel */
> +	u32	drm_format;	/* format in DRM definition */
> +	u32	base;		/* cursor base in graphics memory */
> +	u64     base_gpa;
> +	u32	x_pos;		/* in pixels */
> +	u32	y_pos;		/* in lines */
> +	u8	x_sign;		/* X Position Sign */
> +	u8	y_sign;		/* Y Position Sign */
> +	u32	width;		/* in pixels */
> +	u32	height;		/* in lines */
> +	u32	x_hot;		/* in pixels */
> +	u32	y_hot;		/* in pixels */
> +};
> +
> +struct intel_vgpu_pipe_format {
> +	struct intel_vgpu_primary_plane_format	primary;
> +	struct intel_vgpu_sprite_plane_format	sprite;
> +	struct intel_vgpu_cursor_plane_format	cursor;
> +	enum DDI_PORT ddi_port;  /* the DDI port that pipe is connected to */
> +};
> +
> +struct intel_vgpu_fb_format {
> +	struct intel_vgpu_pipe_format	pipes[I915_MAX_PIPES];
> +};
> +
> +int intel_vgpu_decode_primary_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_primary_plane_format *plane);
> +int intel_vgpu_decode_cursor_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_cursor_plane_format *plane);
> +int intel_vgpu_decode_sprite_plane(struct intel_vgpu *vgpu,
> +	struct intel_vgpu_sprite_plane_format *plane);
> +
> +#endif
> diff --git a/drivers/gpu/drm/i915/gvt/gvt.h b/drivers/gpu/drm/i915/gvt/gvt.h
> index ba53ad1..d0fe4d0 100644
> --- a/drivers/gpu/drm/i915/gvt/gvt.h
> +++ b/drivers/gpu/drm/i915/gvt/gvt.h
> @@ -46,6 +46,7 @@
>  #include "sched_policy.h"
>  #include "render.h"
>  #include "cmd_parser.h"
> +#include "fb_decoder.h"
>  
>  #define GVT_MAX_VGPU 8
>  
> -- 
> 2.7.4
> 

-- 
Open Source Technology Center, Intel ltd.

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